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Home arrow Wafer Processing arrow Articles arrow Edition 14 arrow 14th Edition: Achieving Higher Productivity in Oxide CMP
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14th Edition: Achieving Higher Productivity in Oxide CMP Print E-mail
Feb 02, 2005 at 05:44 PM
CHAD C. GARRETSON, JEFF P. RUDD, BRIAN J. BROWN, DAN FLYNN & STEVE CHEN, Applied Materials, Santa Clara, CA, USA

ABSTRACT

Pioneered by IBM in the 1980s, silicon dioxide was the first application of chemical mechanical planarisation (CMP). As more transistors are packed onto each chip, the number of interconnect levels and the number of oxide CMP wafer passes has increased dramatically. It is common today for 0.18-mm devices to require 5-8 oxide polishes for logic devices and 3-5 oxide polishes for DRAMs. Oxide is today, and is likely to remain for several more years, the largest CMP application. The biggest challenge to developing improved oxide CMP process technology is achieving better process performance with higher productivity and lower cost of ownership (CoO). Consumable choices have a significant impact on oxide CMP process performance and cost of ownership [1-3]. Cost of consumables (CoC) can represent a major portion of the total CoO for oxide CMP, thus reducing CoC by extending consumables life has been a focus of oxide CMP cost reduction efforts. Longer consumable life has the added benefit of minimising the frequency of tool requalification, resulting in higher availability and more product wafers out per week. Also, given the high cost of oxide CMP slurry, reducing slurry usage per wafer can greatly lower overall cost of ownership. This article will present solutions that meet the oxide CMP productivity and process requirements for the 0.13-mm technology node and beyond.
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