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14th Edition: Barriers for Cu/low k Damascene Structures |
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Feb 02, 2005 at 05:41 PM |
KAREN MAEX, ZS. TOKEI, A. SATTA, F. LANCKMANS, W. WU & F. IACOPI, IMEC, Leuven, Belgium
ABSTRACT
The introduction of new dielectrics in the Back End of Line (BEOL)
processes is very challenging. The choice of the low k dielectric has a
large impact on all subsequent steps in the process, i.e. on the
deposition of hard masks, the patterning and strip process and the post
dry etch clean. The mechanical properties of the low k dielectric of
choice are directly related to the Cu deposition and the Cu CMP step.
What is often overlooked is that the compatibility of the barrier with
the low k materials is essential to ensure the diffusion barrier
properties for Cu. In this paper an overview will be given of the
current and future barrier deposition techniques and their
compatibility with current and future low k dielectrics. It is clear
that a barrier integrity test vehicle is mandatory to ensure barrier
quality on the low k material with relevant feature dimensions for the
technology in development.
 Barriers for Cu/low k Damascene Structures
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Wafer Processing 
