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TI tweaks straining & low-k at 45nm, opts for immersion & metal gate but no high-k |
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Jun 12, 2006 at 01:36 PM |
 Texas Instruments has revealed the basic behind its planned CMOS process migration at the 45nm node ahead of the 2006 Symposium on VLSI Technology, held in Hawaii.
TI plans to continue a conservative material and process technology migration from its current leading node offerings at the 65nm node that went into early production at the end of 2005.
In a statement TI plans to continue to push optical lithography and will use 193nm ArF immersion lithography tools for critical layers at the 45nm node. TI's major lithography tool supplier is ASML.
Emphasis as expected is being focused on SoC processors and low power consumption, especially for mobile devices. The company is making strides in reducing the k-value of the interconnect dielectric film, claiming a move to a k-value of 2.5. TI's 65nm process uses an OSG film with a k-value of 2.8-2.9 and up to 11 layers of copper interconnect. This will be TI's third-generation process technology to use low k dielectrics for reducing capacitance and propagation delays, according to the company.
TI's 65nm process employs an induced strain on the transistor channel during chip processing to increase electron and hole mobility. At the 45nm node TI will add further straining techniques as well as employ silicon-germanium in its strain application under the transistor.
However, the company stated that later generations of its 45nm process could include full-silicidation-of-polysilicon (FuSI), or a combination of metal plus a silicide. This would provide further boost to the low power and high performance devices that are expected to required in the future. TI believes that employing a metal gate with silicon nitrided dielectrics delivers the necessary power consumption control without having to simultaneously move to new, more complex high-k materials.
The conservative processes have meant further enhancements will be adopted with regard to design restrictions and enhancements in layout with adjustments to the transistors' gate length, threshold voltage, gate dielectric thickness and bias conditions.
As expected TI will initially fabricate its 45nm devices at its DMOS6 300mm fab. A low-power ASIC design library will be available by the end of this year, with samples of the first SoC product delivered in 2007 and initial production in mid-2008.
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