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TSMC puts together designers DFM tool kit for 65nm devices |
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May 15, 2006 at 02:11 PM |
 Taiwan Semiconductor Manufacturing Company (TSMC) has assembled a 65nm DFM Compliance Design Support Ecosystem that is intended to enable IC designers to use the same DFM data file irrespective of the tool or vendor.
TSMC developed the unified format to align Lithography Process Check (LPC), Chemical Mechanical Polishing (CMP) Analysis and Critical Area Analysis (CAA), to TSMC's manufacturing data format. The year-long project is designed to overcome yield limiting factors common to 65nm designs and rule restrictions.
"This is a comprehensive collaboration to deliver 65nm DFM-compliant products and design services to the designer's desk top," said Edward Wan, Senior Director of Design services marketing for TSMC. "Basically, we've defined what it means to be DFM compliant, and we've helped our Ecosystem partners to achieve that compliance."
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