Dr P.H. Haumesser, Dr S. Maîtrejean & A. Roule, CEA-LETI, Grenoble, France; Dr G. Passemard, STMicroelectronics, Crolles Cedex, France

ABSTRACT

The damascene approach is now well established for the fabrication of advanced copper interconnects. However, as ultralarge integration progresses, process evolutions are mandatory to face the new challenges raised by feature size reduction. In this article, the extendibility of the copper deposition processes at the 32nm node is discussed. The PVD techniques used to grow the diffusion barriers and copper seed will probably have to be replaced by conformal processes. If ALD seems to be a promising solution for barrier deposition, the fabrication of an ultrathin and conformal seed layer is extremely challenging. Several solutions are examined and discussed. For feature filling, electrodeposition will probably remain the standard technique. However, the extension of existing solutions is challenging. What will be the metallization scheme at the 32nm node? This is surely an open question. Two main requirements will guide the selection of a process: the control of the copper/barrier interface, and most importantly the limitation of resistivity increase in the narrow lines.