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The discussion topic format is new to Semiconductor Fabtech. It consists of individual experts in a field providing separate comment on a major technology issue. All contributors' views are presented separately and formatted clearly to show the differences compared to a co-authored style paper.
Walt Trybula, The Trybula Foundation Inc., & Brian Grenon, Grenon Consulting, Christian K. Kalus, SIGMA-C, Nigel Farrar,Cymer Inc., Frank D. Masciocchi, Litel Instruments, Martin McCullum, Nikon Precision Europe, Mircea Dusa, ASML, Rainer Pforr, Infineon Technologies. ABSTRACT
As the lithography is both the most costly and critical process towards fully functioning semiconductor devices, it is obvious that developments within the lithography field are closely followed and analyzed. This year at the SPIE Microlithography Conference it became clear that a major shift in lithography tool and process techniques is required to continue scaling as befits Moore's Law. EUV lithography is not going to be ready for Intel's needs at the 32nm node while immersion lithography has not ‘matured' enough for the chip giant to ‘risk' production for its introduction of 45nm node IC devices. Instead, Intel plans to retain the use of ‘dry' 193nm ArF DUV tools, while adopting a Double Patterning (DP) imaging regime through to the 32nm node. Although there are various DP strategies possible, few experts in the field believe that some form of throughput, cycle-time and cost impact on fab operations will not occur. Although not all leading-edge IC manufacturers may pursue a DP strategy, it would now seem certain that everyone will need to look deeply into the pros and cons before making such critical manufacturing decisions. We are very pleased to have been able to assemble in this discussion piece, a group of experts within the lithography discipline to cover some of the key issues surrounding DP strategies, especially at such short notice, so soon after the SPIE Conference.
29th Edition: Discussion topic: Double Patterning technical concerns and its impact on fab operations
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Comment by GUEST on 2008-03-17 11:25:03
There have been reports of shortages in Intel's 45nm chip supply. Could this be caused by double patterning or something else like high-k? | Comment by GUEST on 2007-12-03 09:51:09
Intel needs other companies to be the front line for immersion lithography at 45 nm before diving in itself at 32 nm. Slick. | Comment by GUEST on 2008-03-10 11:15:54
We'll see if early adoption of double patterning pays off for Intel's 45nm profitability. |
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