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Thermal and mechanical impacts on 65nm devices |
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Apr 24, 2006 at 03:04 PM |
 Researchers at the Crolles2 semiconductor process development alliance in France believe that the move to 65nm CMOS technology and beyond manufacturing processes and the introduction of new materials will have a major impact on the thermo-mechanical performance both in terms of the basic chip and for stacked packages. Stacked systems-in-packages (SiPs) are used in highly condensed products such as mobile phones.
Reduced interconnect dimensions can lead to mechanically induced stress voiding in copper interconnects and cracking of low-k dielectrics. Recent experimental observations suggest that these failure modes can interact, creating the need to improve on previous work where the two effects have been considered separately. ST and Philips researchers at Crolles2 Alliance have developed a thermo mechanical analysis using energy-based failure criteria, where the risk of void nucleation and growth was compared with crack related failure.
The prediction of thermo-mechanically induced failures in electronic packages in early stages, and the understanding of the precise failure mechanisms, is also important for estimating the reliability of stacked devices. The Crolles2 Alliance Assembly (CAA) modeling cooperation setup has developed a set of virtual prototyping techniques for combined design of experiment/response surface modeling (DOE/RSM) techniques to allow the critical variables for each package, in terms of sizes, thickness, and/or material combinations to be explored.
These groups are presenting at this year's IEEE European conference on thermal, mechanical and multiphysics Simulation and Experiments in Micro-Electronics and micro-systems (EuroSimE, http://www.eurosime.org/index.htm), in Como, Italy, April 23-25, 2006. Crolles2 involves STMicroelectronics, Philips Semiconductor, Freescale and TSMC, along with other supporting companies and organizations.
By Dr Mike Cooke
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