|
New Product: Ponte Solutions design-stage yield analysis tool is geared for complex IC’s |
|
|
|
Mar 30, 2006 at 10:58 AM |
 Product Briefing Outline: Ponte Solutions, has announced the availability of "Yield Analyzer" v2.0, featuring a unique model-based analysis technology providing automated yield analysis and enabling optimization of a design prior to its tape-out. Yield Analyzer is claimed to reduce manufacturing cost and time-to-volume production of complex semiconductor ICs by revealing yield-sensitive areas of the design and enable yield improvement at the design stage, prior to committing to production. Yield Analyzer has been validated and is already in use at IDMs, foundries and fabless IC design companies, according to the company.
Problem: With each successive process generation, product yield has become progressively lower. Analysts predict that, without a change in design methods, yields of 65nm designs will stay low and unpredictable. One reason is that designers and manufacturing groups have traditionally relied on design rules as an abstraction of process information. If the designers follow these rules, the manufacturing process should produce an acceptable yield. However, with 130nm and smaller process nodes, this approach began to break down; two different designs that are fully DRC clean, i.e. they both meet the design rules without any violations, result in considerably different manufacturing yield. Lack of visibility into yield problems at the design stage has become the main problem of IC manufacturing at sub-130nm geometries.
Solution: Ponte's model-based approach claims to solve the impending yield crisis while leveraging existing design flows. Ponte's Yield Analyzer addresses yield at every step of the design flow starting from library/IP design and characterization to netlist generation, floorplanning, full chip detailed routing and ECO. Now, designers can analyze the yield sensitivities of their libraries, IPs or full chip designs, in an evolutionary design methodology. Thus, adding yield as the fourth dimension to their design goals, besides area, timing and power. A unique feature is claimed to be the ability to recognize memory structures and taking redundancy into account while reporting yield sensitivities for the memories or for full chip. This allows designers to trade off area versus yield sensitivity.
Applications: All designs from 130nm onwards.
Platform: Unified yield modeling platform that allows integrated approach to yield analysis during design stage. Proprietary third-generation analytical engines for critical area extraction- enables highest possible accuracy to cover all intricacies of nanometer technologies and avoids accuracy loss due to commonly used sampling techniques. The system supports the use different design styles at different design stages, i.e. cell-based and custom and different flows such as library (stand alone and in the context of the design), floorplan analysis and detailed routing analysis using either GDSII or DEF formats or using Open Access interfaces.
Availability: March 2006 onwards.
|
Product Briefings 
