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15th Edition: Selective Removal Strategies for Low k Dual Damascene |
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Feb 02, 2005 at 04:09 PM |
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STEVE LASSIG, SIMON MCCLATCHIE & ADRIAN KIERMASZ, Lam Research Corporation, Fremont, CA, USA ABSTRACT
Materials
and processes for the back end of the line (BEoL) are changing.
Shrinking design rules have continued to increase the number of
interconnect layers required. Strategies to minimise interconnect
delays involve improving conductivity with copper wiring and lowering
the dielectric constant (k) value by employing low k films. While
copper integration is fairly advanced, low k materials present a wide
range of new integration challenges because of their lower density,
inferior mechanical properties, and typically increased organic
content.
In dual damascene applications, they are layered between a
variety of other films. The number of stack combinations and
requirements necessitate developing processes and process systems that
are highly flexible and provide large processing windows. This paper
discusses challenges and strategies for selective removal processes and
equipment for low k integration, including those for etching and
chemical mechanical planarisation (CMP).
 07 - Selective Removal Strategies for Low k Dual Damascene
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Wafer Processing 