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15th Edition: The Case for CVD Low-K Technology |
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Feb 02, 2005 at 04:06 PM |
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MEGGY GOTUACO, PETER W. LEE, LI-QUN XIA & ELLIE YIEH, Applied Materials, Santa Clara, CA, USA ABSTRACT
As
chip manufacturers prepare to implement advanced copper and low K
interconnects, debate continues over chemical vapour deposition (CVD)
versus spin on dielectric (SOD) low-K approaches. Key challenges to
low-K implementation include resist compatibility and selectivity,
resistance to plasma attack during etching and photoresist removal,
adequate adhesion and strength to withstand CMP, wire bonding and
packaging, and overall device reliability. As chipmakers start putting
these films into production, the additional requirements of cost of
ownership and extendibility to the ≤100-nm generation also come into
play. This article presents research data that substantiates the
viability of a CVD low-K film for the production of <0.13-µm devices.
 06 - The Case for CVD Low-K Technology
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Wafer Processing 