Philippe Absil, Serge Biesemans, Jorge Kittl & Anne Lauwers, IMEC, Leuven, Belgium

ABSTRACT

With shrinking device technologies, industry is facing difficulty in reducing the oxide thickness to the required number as set by traditional scaling laws to maintain electrostatic integrity and sufficient drive current. The silicon MOSFET has entered the regime where further scaling of device parameters increases parasitic leakages, particularly the conduction through the gate dielectric. The use of a metal gate allows for scaling the electrical thickness without increasing this gate leakage. In this article, we silicided gates (FUSI) as a path to integrate materials with metal-like properties as gate electrodes on SiO₂ or high-k. A view on CMOS integration achieving proper Vts in both nMOS and pMOS is reviewed.