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Home arrow News arrow Latest News arrow SOISIC Teams with leading foundry to produce industry's first SOI-based ASIC devices
SOISIC Teams with leading foundry to produce industry's first SOI-based ASIC devices Print E-mail
Mar 03, 2006 at 04:03 PM
ImageSOISIC, an integrated circuit subcomponent intellectual property (IP) designer for silicon-on-insulator (SOI) device, announced that one of its leading foundry customers has successfully produced six working integrated circuits (ICs) using an ASIC-based SOI design process. This is designed to open up SOI technology to the fabless semiconductor market. SOISIC, on its first pass, successfully taped-out and validated standard cells with three Vts, Input-Output circuitry and memories, as well as a data encryption and decryption circuit, consisting of 8 million transistors. SOISIC works closely with major electronic design automation (EDA) tool vendors to enhance their tool capabilities.

Previously, the only semiconductor companies able to produce leading-edge SOI devices were integrated device manufacturers (IDMs) with their own multi-billion-dollar fabs and fully custom design methodologies. SOISIC and its foundry customers are making SOI technology available to the fabless ASIC design community by providing IP with design libraries specifically developed to solve SOI design complexities. The IP is said to fit seamlessly into customers' existing design flows, allowing designers to quickly and cost effectively create SOI-based chips.

Eduard R. Weichselbaumer, president and CEO of SOISIC, comments: "Leading IDMs have already demonstrated the performance advantages associated with this innovative technology. In fact, many leading-edge PCs, servers and gaming systems are powered by SOI-based microprocessors. Now with the successful production of SOI-based devices at a top foundry, the stage is set for broader SOI adoption by the fabless design community."

Currently, all the major foundries have announced, or are expected to declare, the future availability of SOI manufacturing processes at the 90- or 65-nm design nodes. Such widespread foundry adoption will increasingly facilitate SOI proliferation in the ASIC/COT (Application Specific Integrated Circuit/Customer Owned Tooling) markets, where several factors are expected to drive adoption.

SOI can boost device performance by as much as 30 percent and deliver power efficiency gains of up to 50 percent over bulk CMOS designs. SOISIC believes that the cost of a finished die on SOI could be competitive or even lower than bulk CMOS processes for many applications at advanced nodes. Equally attractive are the potential system-level cost savings due to the power/performance advantages inherent in SOI-based chips.


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