|
Designs on common platform |
|
|
|
Feb 28, 2006 at 03:12 PM |
 New intellectual property (IP) design support is to be developed for the 65nm common process platform of IBM, Chartered Semiconductor Manufacturing and Samsung. ARM is collaborating with the three companies to offer the ARM Advantage Artisan physical intellectual property (IP) on the 65nm generic Common Platform process, enable multi-sourcing strategies.
In addition, Cadence Design Systems announced immediate availability of a 90nm reference flow that addresses power-management and design-yield issues as part of an ongoing collaboration with IBM and Chartered.
The 65nm development is aimed at extending the support from ARM for physical IP for the IBM and Chartered's jointly developed 90nm Common Platform process. Low-power ARM Metro Artisan physical IP, for IBM, Chartered and Samsung at the 65nm low-power process was announced last year.
ARM Advantage IP provides high-speed, low-power performance to meet a wide range of applications in consumer, communications and networking markets. The Advantage and AdvantageHS standard cells include power management kits that are characterised for multiple transistor threshold voltages. Five Advantage memory compilers are offered with advanced power saving features. The I/O products include multiple configurations supporting 1.8, 2.5 and 3.3V systems. The suite of products is characterised for timing and power over an extended range of voltages, enabling designers to perform pre-tapeout simulation of multi-voltage designs.
The Advantage IP includes ARM's extensive set of views and models providing integration with many of the industry's electronic design automation (EDA) tools. Additionally, the IP incorporates the combined expertise of ARM, IBM, Chartered and Samsung in addressing design for manufacturability of advanced 65nm technology. Complete set of ARM physical IP products are expected to be available second quarter of 2006 for download from ARM's website, free of charge, to customers in the 65nm process.
The Cadence design reference flow is aimed at the 90nm low-power Common Platform process. The new RTL-to-GDSII reference flow is based on the Cadence Encounter digital IC design platform and enables higher productivity and improved quality of silicon (QoS). The reference flow addresses critical low-power design challenges, from chip prototyping through power, timing and area optimisation. The Cadence SoC Encounter GXL RTL-to-GDSII system enables timing-aware leakage power and dynamic power optimisation, using techniques such as multi-supply voltages, multiple-Vt optimisation, and clock gating. This optimisation helps designers improve timing closure and reduce device area, while lowering power consumption without compromising performance.
The flow addresses nanometre defect yield issues with yield analysis and optimisation capabilities embedded in critical implementation stages such as physical synthesis and routing. For yield analysis, full-chip or block-level defect yield losses are assessed based on factors such as critical area and cell yields. An innovative yield prototyping capability enables designers to choose full-chip floorplanning strategies with visibility of yield considerations before committing to a physical architecture for the chip, allowing them informed design choices to speed yield ramp. The growing impact of wiring on final chip yield is addressed by optimising double-via insertion, wire spacing and other factors concurrently during routing, instead of a separate post-processing step.
Cadence, Chartered, IBM and Samsung are working on a reference flow targeted at the Common Platform's 65nm low-power process.
By Dr Mike Cooke
|
News 