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Immersion works at near-zero defects, according to TSMC |
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Feb 22, 2006 at 02:04 PM |
 World-leading foundry TSMC claims that its immersion lithography is nearly production ready and that this has been achieved with proprietary techniques that produce near-zero defect rates. The company's immersion lithography programme has produced test wafers well within acceptable parameters for volume manufacturing, it adds. TSMC researchers will present their results at the SPIE Microlithography Conference in San Jose, California.
Burn Lin, senior director of TSMC's micropatterning division, reports: "Recently, TSMC produced multiple test wafers with defects rates as low as three per wafer -- better than any other immersion results to date, and comparable to the very best dry lithography results. With defect root causes understood, TSMC can now focus on throughput improvement for high-volume manufacturing."
TSMC's R&D researchers say that they have resolved challenges such as bubbles, watermarks, particles, particle-induced printing defects, and resist residue by developing a proprietary defect-reduction technique that, on initial tests, produced less than seven immersion-induced defects on many 300mm wafers, a defect density of 0.014/cm2. Some wafers have yielded defects as low as three per wafer, or 0.006/cm2. This compares to several hundred thousand defects produced by a prototype immersion scanner without these proprietary techniques and significantly better than published champion data in double digits.
TSMC's immersion lithography technology is targeted at 45nm manufacturing.
By Dr Mike Cooke
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