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SEMATECH starts 3D interconnect cost analysis program |
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Feb 09, 2006 at 06:27 PM |
 SEMATECH has started a project to assess the commercial
feasibility 3D interconnect structures for future IC devices. SEMATECH
members have commissioned the study, as it is believed the migration to
low-k materials will not meet process requirements by 2010 and 3D
interconnect structures could be the less disruptive path to successful
volume manufacturing. However, the new study will work alongside
current low-k developments at SEMATECH, which are concentrated on CVD
based solutions.
"The
criteria for analysis will, of course, be cost effectiveness and
functionality/performance enhancement," said Sitaram Arkalgud, director
of SEMATECH's Interconnect Division. "The industry has been pursuing
copper and low-k interconnect technology since the mid-1990s, and true
low-k materials are beginning to move into real products. "However,
decreasing k-effective by constantly changing dielectrics, and often
the assist layers, presents challenges - notably with developing and
requalifying new metals continuously."
A working group of about 20 SEMATECH member
company representatives will assess the key challenges of 3D and the
available options for addressing them.
"Our program will focus on wafer-on-wafer and
die-on-wafer structures," Arkalgud said. "Solutions will be sought for
both high-performance and low-cost products." Interconnect engineers
will utilize the cost model and work with representatives of the
microchip industry to develop consensus on key industry-wide issues, he
added.
IMEC of
Belgium has also been working on 3D interconnect modelling software
(image provided) and processing technology.
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