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TSMC offers 80nm mask shrink of 90nm process |
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Jan 17, 2006 at 02:39 PM |
 TSMC has started volume production of a half-node process for both
graphics chip leaders, ATI and Nvidia at the 80nm node. The shrink of
features has occurred at previous nodes for customers wanting an extra
performance or die cost boost without having to redesign key elements
of the chip.
According to TSMC its 80nm shrink reduces the size of 90nm designed
chips by as much as 19 percent, giving as much as a 20 percent
reduction in the cost of die.
With this process, designers can improve performance and reduce the
overall size of their designs by up to 19 percent, resulting in more
die per wafer and more than 20 percent cost-per-die reduction.
"NVIDIA and TSMC have a longstanding strategic collaboration involving
half-node technologies," said Chris Malachowsky, Senior Vice President
of Engineering and Operations, NVIDIA. "The ability to quickly port a
design to a new technology with higher performance and a smaller
footprint is a powerful tool in a competitive, consumer oriented
market."
TSMC's high-performance GT process as used by the graphics chip
companies is the first to enter production. In the following months
TSMC plans to offer its high-speed HS process and low power LP
processes at the 80nm node by March 2006. A special GC process, which
provides both low active and standby power advantage, will become
available in the third quarter of 2006, according to the company.
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