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Tool Orders: Cypress's R&D fab selects Semitool's Raider SP cleaning system |
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Dec 12, 2005 at 07:24 PM |
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Cypress Semiconductor's Silicon Valley
Technology Center has installed a Semitool
Raider(TM) SP single wafer process system for the
development of advanced cleaning processes to support 65- and 45-nm technology,
as well as for the production of current and next generation devices.
"Our decision to adopt single wafer cleaning
technology as part of our R&D and manufacturing strategy is driven by
several key factors including the need to achieve maximum yield in the shortest
time, defect reduction, low cost of ownership, and extendibility to more
advanced device nodes," said Bert Bruggeman, managing director of SVTC.
"The Raider gives SVTC the capability and flexibility to develop new,
innovative cleaning technologies while at the same time delivering
state-of-the-art performance for our customers' current generation of
devices."
SVTC enables third party engineering groups to take
their silicon-based technologies from proof-of-concept to manufacturing through
a state-of-the-art toolset in a 16,000 square-foot clean room in Silicon
Valley.
"The Raider installed at SVTC will allow Semitool
and Cypress to develop and deploy surface preparation processes to meet the
challenges of future device design nodes," said Dana Scranton, Semitool's
vice president for Surface Preparation Technology. "Our near term focus is
on 65- and 45-nm, while at the same time looking toward 32-nm design rules and
what will be required to address the cleaning challenges at that node. An
important element of our partnership with the SVTC is having access to their
resources, which will facilitate more rapid development and deployment of next
generation FEOL and BEOL processes."
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