By Dr Mike Cooke

Toshiba and Sony announced development of carrier mobility enhancement and wiring process technology for boosting LSI performance at 45nm. Current drive performance has been improved through strained silicon technologies, enhancing carrier mobility. Further, a low-k film has been developed as inter-metal dielectric.

In fact, the researchers have made two advances in strained silicon - first optimizing the thickness of a stress liner covering the transistor and second bringing global stress into the device substrate. The stress liner improves current drive performance by some 40%, according to the companies. The global stress is achieved through a low cost process that improves current drive performance by around 20%.

In seeking improved low-k film technology, Toshiba and Sony enhanced the quality of the low-k film by appropriately allocating dummy wiring to improve removal of moisture from the film. In doing so, they overcame the problem of poor drain characteristics in low-k film.

Strained silicon technologies fall into two categories: local strained methods and global strained methods. Local strain enhances the mobility of carriers by forming a stress liner on top of transistors. While a thicker stress liner was recognized as bringing better transistor performance, Toshiba and Sony confirmed that, in a circuit layout of many transistors, exceeding a certain thickness prevents the stress enhancement from being transmitted to each transistor. This results from stress diffusion by unification of the stress liner of proximate transistors. Studies confirmed that the optimum stress liner thickness in 45nm circuits is 30nm. At that thickness, current drive performance was found to be improved by 15% at nMOSFET and by 60% at pMOSFET, in combination with eSiGe technology.

Global strained silicon technology makes use of a special silicon substrate embedded with stressed SiGe film throughout the substrate. Toshiba and Sony had already developed a strained silicon technology that horizontally rotates the silicon substrate by 45 degrees to enhance total transistor performance. This makes a difference because silicon has different electrical properties in different directions. The more conductive directions are different for each carrier type, electron or hole. Drawing on this, the two companies improved nMOS performance by producing a device on strained silicon substrate and embedding silicon in recessed Source/Drain of SiGe layer with epitaxial growth, causing tensile stress. This improved current drive performance by approximately 20% on average.

Despite the difficulties in implementing ultralow-k in previous generations, it seems to be making a comeback at 45nm, where porous materials are regarded as a promising route to performance enhancement. The initial concern about introducing porous materials is potential deterioration in device solidity. According to Toshiba and Sony, an efficient solution was found in a hybrid structure that use layers of organic and inorganic materials, which was introduced from the 65nm generation. Another bigger concern was increased resistance and performance deterioration from a build up of moisture in the porous materials. This was solved by adoption of a layout that allocates dummy wiring around the via. This helps to release moisture from the porous materials, preventing oxidization of metal at the via.

Toshiba and Sony announced details of the technologies at the International Electron Devices Meeting (IEDM) in Washington, DC.