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IBM planning 22nm photomask development with immersion lithography
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Although EUVL remains the favored choice by lithography experts for
semiconductor imaging at the 22nm node, according to attendees at the
3rd SEMATECH Litho Forum in May, IBM and Toppan Printing have said that
they are now collaborating on all phases of 22nm photomask process
development using 193nm ArF immersion lithography technology.
Initially, the two companies started development of photomask
fabrication processes for the 45nm node in 2005 that was followed up
with a 32nm agreement in 2007.
“This newest agreement will help ensure we can continue to deliver
innovative chip applications for IBM systems and our OEM semiconductor
clients,” said Michael Cadigan, General Manager, IBM Semiconductor
Solutions. “This collaborative effort builds upon our joint progress at
45nm and 32nm and sets us on a path to deliver the photomasks needed
for next-generation chip manufacturing production.”
Toppan
sees the collaboration with IBM as a way to reaffirm itself as the
leading photomask manufacturer as the processes developed for these
leading-edge nodes can be transferred to mask shops around the world.
“We
believe this joint initiative will place IBM and Toppan Printing at the
forefront of advanced photomask technology development, and thus will
enable us to contribute to the technological innovation in the world’s
semiconductor industry,” commented Naoki Adachi, President of Toppan
Printing. “Toppan Printing is the only photomask manufacturer in the
world with the capability of providing high-quality photomask products
in a timely manner in the U.S., Europe, Japan and other Asian
countries.”
IBM and Toppan said in a statement that while the
industry considers EUVL and other technologies such as nano-imprinting
techniques for the 22nm node and below, many technical hurdles remain.
This
indicates that the use of immersion lithography at the 22nm node -
while not ideal due to imaging limitations and significant increases in
mask costs due in part to the need for double patterning - is ensuring
that device scaling can continue until a replacement technology is
ready for adoption.