By Dr Mike Cooke

UMC's Central Research and Development Division (CRD) has successfully developed technology to simultaneously enhances NMOS and PMOS device performance. The "Ultimate Spacer Process" (USP) results in devices showing drive current improvements of 15% for NMOS and 7% for PMOS, says the Taiwan foundry.

"Seeking ways to enhance electron and hole mobility is a major focus for device development at UMC," says Dr. Mike Ma, deputy division director of Exploratory Technology for UMC CRD. "The USP technology enables UMC to provide an extra performance improvement option to complement our other mobility enhancement technologies. With only one additional process step inserted, USP also delivers a manufacturability advantage over other strained silicon technologies."

Combining USP with substrate orientation engineering resulted in a 35% PMOS drive current enhancement. This USP technology has also been successfully deployed in a customer FPGA product, resulting in a 15% speed improvement without compromising yield and reliability performance. UMC claims that this confirms the readiness of applying USP technology for 65nm mass production and beyond.

UMC presented a detailed report of this technology at the International Electron Devices Meeting in Washington, DC.