By Dr Mike Cooke

NEC has developed a 45nm node LSI interconnect technology aimed at improved reliability and low- power consumption. It is hoped that the combination of this interconnect technology with high performance 45nm node CMOS transistors will realize a 50% in chip size with more than 20% reduction in power consumption than those of 65nm devices. NEC is aiming at technology for applications such as high-speed network servers and multi-function mobile terminals with low-power consumption.

The quality of the copper interconnect material is improved through a process involving a low oxygen content (LOC) Cu-alloy conductor with a Ta barrier used as an absorber of oxygen atoms. Oxygen is removed from the Cu interconnects by a physicochemical reaction. The absorber layer is then removed. The reduction in oxygen content of the interconnect ensures reliability of the fully-scaled down interconnects equivalent to that of the 65nm generation.

When the cross-section of interconnects is shrunk, the probability of open failures in the thin Cu lines is increased by mechanical and electrical stresses. The Cu interconnects consist of a polycrystalline structure with many small grains, whose boundaries are potential open failure sites. The companies' research indicated that the metal oxide in the Cu interconnects also induces the open failures.

Another improvement in the chip wiring structure is achieved through a dramatically thinned, dual-damascene (DD) structures in new molecular-pore-stacked (MPS) low-k film. This suppresses parasitic capacitance and, hence, reduces power consumption., NEC claims that the capacitance is suppressed to the lowest levels in the world. Interconnect power consumption was decreased 24% compared to the 65nm node. Dielectric reliability was kept equivalent to that of the former 65nm-node with a low-damage etching process for the low-k material, and side-wall protection of the line-trenches through an ultra-thin polymer film.

Device shrinks narrow the interconnect spacing and unfortunately increase the parasitic capacitance. The narrow spacing also makes it harder build robust interconnects, maintaining product yields. Techniques to reduce power consumption of interconnects include introduction of dielectric materials that store minimal charges, such as low-k films, and the minimization of the charge store area between the lines by reducing the line height.

The MPS low-k film (k=2.4) was development in collaboration with its NEC Electronics subsidiary and Japan's MIRAI semiconductor research project. The film can be deposited by high vacuum simply by adjusting the deposition time.

The partners presented the 45nm- interconnect technology at the International Electron Devices Meeting (IEDM), December 5-7, Washington, DC.