By Dr Mike Cooke

Joint development at IBM and AMD has resulted in the successful combination of embedded Silicon Germanium (e-SiGe) with Dual Stress Liner (DSL) and Stress Memorization technology (SMT) on Silicon-On-Insulator (SOI) wafers. According to the researchers, this has resulted in a 40% increase in transistor performance compared to similar chips produced without stress technology, while controlling power consumption and heat dissipation.

The new process technologies reduce interconnect delay through the use of lower dielectric constant (lower-K) insulators to improve overall product performance and lower power consumption. In addition, the new technologies have shown ability to be manufactured at the 65nm generation and scaleable for use in future generations, say the companies.

"At IBM, we strongly believe that our unique joint development partnership with AMD at East Fishkill, NY, is key to overcoming power and heat challenges as the industry reaches near atomic scales," says Gary Patton, vice president, technology development at IBM's Semiconductor Research and Development Center.

Additional details about third generation strain technology innovations from AMD and IBM will be disclosed at the International Electron Devices Meeting, December 5-7, 2005 in Washington, DC. This technology was developed at AMD's fabrication facilities in Dresden, Germany, and at the IBM Semiconductor Research and Development Center in East Fishkill, NY.