By Dr Mike Cooke

Texas Instruments reports that it has qualified its advanced 65nm process technology eight months after delivering first samples of a wireless device and is moving to volume manufacturing. TI first disclosed details around its advanced 65-nm CMOS process in early 2004, and announced sampling of the wireless digital baseband processor in March 2005.

The 65nm process includes up to 11 layers of copper interconnect integrated with a low k dielectric (OSG, k=2.8-2.9). Other improvements include an induced strain on the transistor channel during chip processing to increase electron and hole mobility; nickel silicide to lower both gate and source/drain resistance, and ultra-shallow source/drain junctions.

The process technology doubles transistor density over the company's 90nm process, shrinking equivalent designs by half and boosting transistor performance by up to 40%. TI's technology is designed to reduce leakage power from idle transistors and to integrate hundreds of millions of transistors that support both analog and digital functions in System on Chip (SoC) configurations.

The 65nm platform includes TI's SmartReflex technology, a combination of intelligent and adaptive silicon, circuit design and software designed to solve power and performance management challenges at smaller process nodes.

One SmartReflex method monitors circuit speed to dynamically adjust voltages to meet performance requirements without sacrificing overall system performance. The aim is to minimize power usage for each operating frequency, extending battery life and reducing the amount of heat produced by the device.

Other SmartReflex techniques to reduce power leakage include back-biasing of SRAM memory blocks and retention flip-flop circuitry, allowing voltages to drop extremely low values without needing a rewrite of logic or memory content. Together, the SmartReflex package can deliver up 1000 times reduction in power leakage, according to TI.

TI offers several process technology recipes; including very low power for extended battery life in portable products; a mid-range offering for DSP-based products; and TI's high performance ASIC library geared toward communications infrastructure. The highest performance version of TI's 65nm process supports server-class microprocessors.