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Home arrow News arrow Latest News arrow Scaling conventional bulk planar MOSFETs to 2020
Scaling conventional bulk planar MOSFETs to 2020 Print E-mail
Dec 05, 2005 at 05:32 PM

By Dr Mike Cooke

NEC reports that it has built scaled sub-10nm conventional bulk planar MOSFETs with an improved on-off ratio. The new device technology has been enabled through a new elevated source/drain extension (SDE) structure achieved through special epitaxial growth techniques.

The SDE structure was created through a silicon selective-epitaxial growth enabling a decrease in the effective junction depth. The silicon surface for the source/drain doping region was raised with respect to the channel region surface. The thicker, elevated SDE region realizes a reduction in parasitic resistance and an enhancement in on-current.

By applying a tunneling epitaxial growth technique to the gap region between the silicon-surface and sidewall-material, the thickness of the elevated SDE can be self-aligned and easily controlled. This reduces fluctuations in the elevation thickness, and improves productivity through ease of manufacturing.

The technology can also be used to realize low power, high performance system ICs for the 45nm technology generation and beyond.

Aggressive scaling of silicon device technology has been hampered by the need to make source/drain junctions shallower to ensure steady operation - hard to achieve with current doping techniques. Further, a shallower layer is more resistive to electrical conduction.

The new technique simultaneously achieves controlled elevation of the source/drain region and a significant improvement in the on-off ratio, even for sub-10nm planar bulk transistors. NEC has even fabricated 6nm test- transistors.

NEC believes that this new research development proves the potential for continuous and further technological advancement of system-on-silicon LSI until 2020 through highly reliable, low-cost planar bulk technology. This goes against the view that the standard industry transistor structure will have to change from CMOS to ultra-thin body SOI (silicon-on-insulator) or some double-gate structure,

The results of this research will be announced at the International Electron Devices Meeting (IEDM) in Washington, DC, December 5 -7, 2005.


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