By Dr Mike Cooke

Europe's STMicroelectronics has lined up its contributions in 13 papers at this year's International Electron Devices Meeting (IEDM) in Washington, DC, (December 5-7, 2005). The company highlights its presentation of a 65nm NOR Flash technology with a cell size of 0.042 square micron, claimed as a ‘world's first'. The company also sees a heterojunction bipolar transistor (HBT) architecture as enabling development of low-cost, high-performance RF CMOS-based platforms.

The new ST NOR Flash process can be used in 1-bit/cell and 2-bit/cell configurations. The technology uses cobalt salicide and three copper metallization layers enabling integration of a 65nm NOR Flash array with low-voltage CMOS logic for 1.8V applications. Non-volatile memory scaling and reliability also form the topics for two more ST collaborative contributions to the conference.

The ‘low-cost' HBT is built on silicon germanium carbon (SiGeC) material grown on either bulk silicon or silicon-on-insulator (SOI) substrates. The new device can be fabricated by adding only four masks to the core CMOS process. A fragmented emitter layout minimizes the resistance of an all-implanted collector. Reported performance indicators include fT/fmax as high as 230/240GHz.

ST Crolles, together with CEA-LETI and other research partners, will present a paper on the fabrication of ultra-short channel strained-Ge pMOSFETs for high-performance dual-channel CMOS. Experimental results demonstrate an enhancement in hole mobility with a thin high-k gate dielectric, achieved by optimization of the strained Si and Ge heterostructure.

As a member of the Crolles2 Alliance, ST will also be presenting results with its main partners Philips and Freescale. These include first operational SRAM cells featuring NiSi Totally Silicided (TOSI) gates on an industrial CMOS technology; an enhanced Trench First Hard Mask (TFHM) backend architecture for the integration of advanced low-k dielectric films on 65 nm technology and below; the use of a 475°C+ anneal to repair charge damage in HfO2/TiN stacks; and the potential of Laser Spike Annealing (LSA) for CMOS scaling, enabling the effective integration of 30nm devices into a 45nm bulk CMOS platform.