Product Briefing Outline: KLA-Tencor has unveiled what it claims
to be the industry's first full-chip process window inspection system
for post-RET reticle design layout inspection. "DesignScan" is intended
to reduce the number of mask design respins needed to achieve a
high-yielding design, resulting in better parametric design performance
and faster time-to-market. DesignScan is especially suited for 90-nm
and below designs, where lithography process windows are extremely
small and problematic. Several leading integrated device manufactures
(IDMs), foundry, and fabless chipmakers are currently evaluating
DesignScan, according to the company.
Problem: Lithography today requires the addition of extremely
complex RETs, such as OPC features, to mask layouts in order to achieve
successful patterning. After OPC is added to the design, it must be
inspected to ensure it is free of design errors that can lead to
patterned defects, as well as to ensure it provides a reasonable
process window for a specific design in a given process, before the
mask is made. Detecting these errors as early as possible is critical,
since a design error found before mask production may take a few days
or a week to correct, yet an error that goes unchecked until wafer
inspection in the fab can result in one or more months of cycle time
delay.
Solution: DesignScan utilizes a unique and proprietary
calibration methodology. Inspection can be run across the full process
window at arbitrarily chosen focus exposure points employing a single
calibration. An 8-mm x 8-mm wafer scale reticle layout can be inspected
across nine focus exposure points in approximately two hours,
acccording to the company. In contrast, existing OPC and verification
empirical models must be calibrated at each focus-exposure condition.
The proprietary calibration process and physics-based modeling result
in significantly reduced calibration burden for the user and superior
model accuracy. In addition, unlike empirical models, the DesignScan
models do not need to be recalibrated for a change in the design
polygons or the RET applied to the design. Further small process
changes, such as a new stepper numerical aperture (NA) setting, do not
require recalibration of the models. For a typical design, DesignScan
inspection can cost less than $500 and the inspection can be performed
concurrently with the mask tape out process, the company states.
Applications: 90nm and below technology nodes.
Platform: Physics-based modeling for greater accuracy and reduced
calibration burden DesignScan is built on a reliable imaging computer
platform that has been field proven and implemented across several of
KLA-Tencor's leading-edge inspection systems. It utilizes physics-based
models to accurately simulate how the design will be transferred to the
reticle layer and how that reticle will be imaged into the resist. The
simulated images are then compared to the desired designed patterns,
and defect detection algorithms are applied to determine if any
unacceptable variation in the pattern occurs within or beyond the
nominal process window.
Availability: October 2005 onwards
Further Information: Product Manager: Gaurav Verma
ph
+1-408-875-0911
email-
Lithography 
Product Briefing Outline: KLA-Tencor has unveiled what it claims
to be the industry's first full-chip process window inspection system
for post-RET reticle design layout inspection. "DesignScan" is intended
to reduce the number of mask design respins needed to achieve a
high-yielding design, resulting in better parametric design performance
and faster time-to-market. DesignScan is especially suited for 90-nm
and below designs, where lithography process windows are extremely
small and problematic. Several leading integrated device manufactures
(IDMs), foundry, and fabless chipmakers are currently evaluating
DesignScan, according to the company.
kla design scan
