|
19th Edition: Scaling plasma-nitrided dielectrics to the 65-nm node |
|
|
|
Jan 21, 2005 at 10:45 AM |
P.A. Kraus, C.S. Olsen, K. Ahmed, T.C. Chua, R. Zhao, F. Nouri, & J. Cushing, Front End Products Group, Applied Materials, Inc., Santa Clara, CA, USA
ABSTRACT
Many technical and manufacturing challenges exist
for scaling gate oxide dielectrics to 65 nm. Plasma nitridation of the
gate oxide has demonstrated advantages in nitrogen dose and profile
control over other nitridation methods. Improvements in the
plasmanitridation process have been developed that result in improved
device performance, including reduced threshold voltage shifts, reduced
mobility degradation, and improved reliability. Clustering the gate
oxidation, nitridation, post nitridation anneal, and poly deposition
has also been demonstrated to reduce EOT, improve within wafer EOT
uniformity, and enhance drive current over non-clustered processing.
These improvements lead to scaling the plasma nitridation process to
the 65-nm technology node.
 09 - Scaling plasma-nitrided gate dielectrics to the 65-nm node
|
Wafer Processing 
