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Jul 21, 2003 at 10:58 AM |
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Mohamed Saleem & Sowmya Krishnan, Ultra Clean Technology ABSTRACT
Several semiconductor processing steps, such as rapid thermal processing (RTP), oxidation, photoresist strip/ashing, post-metal etch passivation, utilize steam to accelerate growth rates or removal rates. In RTP and oxidation processes, the use of steam as a process gas provides the ability to grow thin, highquality dense oxides that have fewer defects and exhibit low interfacial stresses. In photoresist strip processes, controlled addition of a small amount of steam has been shown to improve the ashing rates and facilitate the removal of sidewall residues. Write Comment (0 comments) |
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Jul 21, 2003 at 10:56 AM |
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Interview : J. R. Bertucci & P. Blackborow, MKS Instruments
ABSTRACT Following on from the lead article by John West of VLSI Research in Semiconductor Fabtech 18, in which the market researcher highlighted the emergence of the new ‘critical sub-systems' business model, we take a more detailed look at one of the largest and tightly integrated sub-systems suppliers, MKS Instruments, in an effort to highlight the advantages this brings to chip manufacturers and tool suppliers. Write Comment (0 comments) |
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Mar 21, 2003 at 02:58 PM |
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Charles Ortloff, CTC/United Defense, Santa Clara, California, USA ABSTRACT Erosive wear in slurry delivery circuitry is a source of particulate matter that may add contaminants into CMP processing streams. Using wear reduction methods developed from the oil and gas industries for piping networks, methods to predict and mitigate erosive wear are described that have application to fluid circuitry used for FAB applications Write Comment (0 comments) |
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Mar 21, 2003 at 02:54 PM |
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Steve Holland, Techcet Group, LLC, USA ABSTRACT Chemical Mechanical Polishing (CMP) has become a pervasive process used inmanufacturing virtually every sub-0.25 um generation semiconductor wafer that has a multilevel metal structure. CMP is generally considered to have a high cost of ownership due to the high consumables, and specifically slurry, cost. This article describes technologies that lower cost by delivering precise and reproducible amounts of slurry to the pad. No longer do chip manufacturers have to use excess slurry flow to insure a minimum slurry flow. There is also antidotal evidence from early adapters of controlled slurry flow devices that using reproducible amounts of slurry can enhance the wafer yields. Furthermore, improved slurry or chemistry metering to the CMP tool will allow optimizing the slurry used by process, or even at different steps of the process. These new flow controltechnologies allow controlled flow without compressive action on the slurry and without any obstruction to the flow, thus greatly reducing the risk of defect generation or particle agglomeration. Write Comment (0 comments) |
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Mar 21, 2003 at 02:48 PM |
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John West, VLSI Research ABSTRACT In recent years equipment manufacturers have increasingly looked to their supply base for the design and engineering of subsystems and components for their products. At the same time we’ve seen the end users of equipment also taking advantage of these companies’ expertise to improve the productivity and performance of their installed tools. Both these trends have contributed to the subsystem industry’s raised profile beyond that of mere suppliers of components. Write Comment (0 comments) |
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Mar 21, 2003 at 02:41 PM |
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Scott Robichaud & Katsuhiro Ohnishi, Asahi ABSTRACT Chemical Mechanical Planarization (CMP) slurry systems have created many new challenges in the semiconductor fabrication industry. Certain types of CMP slurries consisting of suspended solids in solution are abrasive, and traditional components used in wet process systems, such as diaphragm valves, can damage these slurries. Write Comment (0 comments) |
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