BRUNO GEOFFRION, ANJANA PATEL, STEVE KIM, MUHAMED RASHEED, NAREN DUBEY, KEN LAI, JOE D'SOUZA, PADDY KRISHNARAJ & MANOJ VELLAIKAL, Applied Materials, Santa Clara, CA, USA

Anew 300 mm HDP-CVD process has been designed to meet the requirements of the 0.10 µm technology node and below. Processes have been developed for shallow trench isolation (STI), pre-metal dielectric (PMD) and inter-metal dielectric (IMD) gap filling that meet 0.10 µm technology node requirements. This article examines the HDP-CVD process improvements and their impact on gap fill and productivity at sub-0.10 µm with aspect ratios greater than 6:1.

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ANANTHA SETHURAMAN, SAGAR A. KEKARE, RAMAN NURANI & DADI GUDMUNDSSON, KLA-Tencor Inc., San Jose, CA, USA

The move to a smaller design rule and the associated processing methods are automatic by-products of the demand for ever more powerful ICs. As a result, there are some anticipated yield management challenges. Coinciding with the most recent IC design rule reduction is the long-awaited transition to 300 mm processing, which presents several unique yield management problems not emphasised before. Some of the process control and defect inspection methodology challenges associated with the 300 mm transition are summarised, and the fundamentals of surmounting them are discussed. Key conclusions are the potential emergence of new defect inspection points and the importance of including yield management in the fab planning process from the beginning.

Prashant Majhi, (Assignee from Philips Semiconductors), Huang-Chun Wen, Gennadi Bersuker, George Brown, Byoung-Hun Lee, (Assignee from IBM), & H. Huff, SEMATECH, Austin, Texas, USA

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The economics of IC manufacturing has driven the decrease of device sizes, while increasing the wafer size to bring down the cost per function for both mixed signal and digital processes. The cornerstone of all logic circuits, the transistor gate stack module, has been successfully scaled for about two decades using conventional materials, SiO2-type gate dielectric and poly-Si gate electrode. However, SiO2-type materials are reaching their physical limits of scaling due to high gate leakage associated with the direct tunneling of the carriers between the electrode and substrate, which is the dominant leakage mechanism in the case of ultrathin dielectrics. 

Halbert Tam, JSR Micro, Inc., Sunnyvale, CA, USA & Nobuo Kawahashi, JSR Corporation, Yokkaichi, Japan

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For Cu/low-k integration at 65 nm or beyond, development on soft CMP polishing is essential to minimize the defectivity. While conventional approaches to defect reduction involve using lower polish pressures, lower polish speeds and slurry filtration to control particle-size distribution, more fundamental changes in CMP consumables may be necessary to provide solutions for the 65-nm node and beyond. To meet these more stringent defect requirements, JSR has developed a low-defectivity CMP process through engineering of a soft abrasive slurry and a polymer-based solid pad. This article will present this approach to defect reduction through design of CMP consumables. Data will be shown that, by design, the compressible nature of the abrasive and soft top layer of the solid pad enable low-defect polishing while maintaining high copper removal rates and planarization capability.

Ken Sautter, KMS Enterprises, Stuart Allen & Bill Moffat, Yield Engineering Systems Inc., San Jose, CA, USA

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In any robust microcircuit manufacturing environment, processes and equipment have to be decided on quickly, often too quickly for all the factors influencing the decision to be properly analyzed. One such process and piece of equipment is in the copper annealing area. This paper is an attempt to cover the process, physical and economic parameters that govern the decision to purchase a copper annealer. The traditional R&D unit, the hot plate, quickly moves to the vacuum hot plate. Then, as the process parameters for circuits with high aspect ratio trenches and problems with electromigration become apparent, a move to some batch process is indicated [1–4]. Further, problems with copper hillocks drive the annealing processes to longer times and possibly lower temperatures. As it was common to fight aluminum hillocks when we started aluminum multilayer metal, similar problems with copper processing should have been expected [5–7]. Problems with copper oxidation push for as low an oxygen concentration as possible [8, 9]. Problems with fluorine contamination determine the need for a totally moisture free environment [10]. Polymer voiding problems also point to a need for longer processing times and possibly some more forceful means of reducing or removing voids created during copper annealing [11, 12].

Dr. Liang Chen, General Manager, CMP Division, PPC Product Business Group, Applied Materials Inc, USA

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Chemical mechanical planarization (CMP) has become a key enabling technology for semiconductor fabrication [1]. Conventional CMP uses slurry, a resilient polishing pad and down force on the wafer to planarize multiple device layers. This makes possible chips with >8 metal layers and 90nm features. New materials, such as copper (Cu) interconnect and low-k dielectric films, are replacing traditional Al and SiO2. These offer the lower RC delay values required to gain higher performance and continue progress on Moore's Law. Yet issues are developing for conventional CMP, especially with advanced 65nm devices, which can employ up to 11 metal layers. Continued device scaling, following Moore's Law, necessitates tighter planarization and process control range at each technology node to meet integration requirements. Additional dielectric polishing, called “overpolish,” could be used to gain better overall uniformity. Although this approach helps to meet the closer limits desired, it adds to the Cu loss and reduces the overall layer thickness. Furthermore, it might not be feasible for ultralow-k dielectrics that need to retain a protective capping layer.

P. H. Haumesser, M. Cordeau, S. Maitrejean & T. Mourier, CEA-LETI and L. G. Gosset & W. F. A. Besling, Philips Semiconductor Crolles R&D and G. Passemard & J. Torres, STMicroelectronics

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As ultra-large scale integration progresses, efficient copper metallization of the narrow geometries becomes challenging. In this article, the various critical steps of the damascene metallization scheme are identified. Barrier deposition, copper seeding, electroplating and copper lines capping are discussed. For each step, current approaches and related limitations are presented. The main purpose of this contribution is to show that electrochemical wet processes can be efficiently used to address the challenges raised by feature size diminution.