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Feb 03, 2005 at 12:01 PM |
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VISWESWAREN SIVARAMAKRISHNAN, PRAVIN NARWANKAR, HELEN ARMER,
PATRICIA LIU, JUN ZHAO & RAVI RAJAGOPALAN, Applied Materials, Inc.,
Santa Clara, CA, USA ABSTRACT
Gigabit
DRAMs will be fabricated with feature sizes <0.13 µm, with cell size
equal to 0.14 µm2 and capacitor area equal to 0.051 µm2. These require
alternative high k dielectric materials in place of silicon oxide and
silicon nitride. The most promising high k dielectric candidate for
sub-0.13 µm design rule devices is tantalum pentoxide (Ta2O5). This
article discusses issues associated with implementing high k dielectric
solutions, including Ta2O5 dielectric deposition, remote plasma
oxidation and crystallisation of the Ta2O5, TiN top electrode
formation, nitridation of polysilicon, and production worthiness issues
of the process.< Write Comment (0 comments) |
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Feb 03, 2005 at 11:59 AM |
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A. KARAMCHETI, V.H.C. WATT, H.N. AL-SHAREEF, T.Y. LUO, G.A. BROWN, M.D. JACKSON & H.R. HUFF, International SEMATECH, Inc., Austin, TX, USA ABSTRACT
Silicon
dioxide (SiO2) may be phased out of its role as the gate dielectric in
a transistor at the sub- 100 nm technology generation. Its impending
departure has brought about an unprecedented industrywide effort to
identify a replacement. While it is possible that one or more of a host
of new materials with a higher dielectric constant (high-K) such as
Ta2O5, TiO2, BST, ZrO2, HfO2, ZrSiO4, HfSiO4, etc., may be utilised,
integrating these dielectrics into a conventional CMOS process is
challenging. Write Comment (0 comments) |
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Feb 03, 2005 at 11:54 AM |
FRANCOIS J. HENLEY & MICHAEL I. CURRENT, Silicon Genesis Corporation, Campbell, CA, USA
ABSTRACT
A
novel technology using atomic layer cleavage has been developed which
allows Silicon-on-Insulator processing to be available for many
substrate materials. The use of SOI technology is discussed and the
atomic cleaving process is described in detail. The advantages of the
process to the field of device manufacture are illustrated.Write Comment (0 comments) |
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Feb 03, 2005 at 11:52 AM |
STEPHEN ST. ONGE & MARK DUPUIS, IBM Microelectronics Division, Essex Jct, VT, USA
ABSTRACT
A
retrospective look at the many years of development and production of
silicon germanium (SiGe) processing reveals significant challenges that
have been overcome to make this the mature technology it is today.
Development of the SiGe EPI process was the fundamental achievement
that made this technology possible. Optimising the interaction of this
EPI layer with its surroundings has enabled the achievement of high
bipolar device yield. Integrating this high performance SiGe HBT with
dense CMOS logic and a complement of passive devices creates
technologies which are well suited for a broad range of products. Using
a modular integration approach enables quick migration to next
generation and derivative technologies. Write Comment (0 comments) |
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Feb 03, 2005 at 11:07 AM |
ALAIN R. COMEAU, Microsemi Corp., Carlsbad, CA, USA
ABSTRACT
When
I started to write this article I put down on three pages the outline
of the subjects I wanted to discuss. Interestingly enough the outline
started with a long list of knowledge and skills one should have to be
as efficient as possible in mixedsignal yield improvement. Only at the
third page did I consider defining what mixed-signal products even
were! I guess this set the tone. In this article we will mostly discuss
people skills (sorry, techies!). In a high tech world where marketing
is oriented towards equipment, machines, device and product
performances, etc., we will talk about people. But first, in order to
set up the proper background, let me start at the end.Write Comment (0 comments) |
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Feb 03, 2005 at 11:05 AM |
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THOMAS EHMANN, LASZLO FABRY, JAMES MORELAND & JÜRGAN HAGE,Wacker Siltronic AG, Burghausen, Germany MARIA SERWE, Agilent Technologies GmbH, Waldbronn, Germany ABSTRACT
Crystalline
perfection and cleanliness of silicon wafers are becoming limiting
factors for increasing integration density of semiconductor devices.
Both crystalline perfection and cleanliness of the wafers depend upon
the cleanliness of process chemicals, process environment and process
variations. Monitoring process hygiene requires sophisticated
ultratrace microanalytical techniques that are capable to control
process cleanliness and to assure product quality down to the lower
ppt-range (pg/ml) [1,2]. As a rule of thumb, reference materials,
analytical environment and analytical chemicals must be one order of
magnitude cleaner than the process conditions to allow dependable
analytical results on processes and products. Write Comment (0 comments) |
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Feb 03, 2005 at 11:03 AM |
ANKUSH OBERAI & SAMUEL TAM, Knights Technology, Sunnyvale, CA, USA
ABSTRACT
In
the highly-competitive LCD manufacturing business, small percentage
differences in yields can spell the difference between success and
failure. By applying the same automated yield management tools that
have been available for years to the semiconductor industry,
manufacturers can increase yields by rapidly identifying specific
problems in their production lines. LCD manufacturing poses a number of
unique problems not present in the semiconductor industry, and these
challenges must be solved to create a useful yield management system.
LCD and semiconductor manufacturing share some similar features. Write Comment (0 comments) |
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Feb 03, 2005 at 11:01 AM |
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KENNETH W. TOBIN & THOMAS P KARNOWSKI, Oak Ridge National Laboratory1, Oak Ridge, TN, USA FRED LAKHANI, International SEMATECH, Austin, TX, USA ABSTRACT
As
integrated circuit fabrication processes continue to increase in
complexity, it has been observed that data collection, retention, and
retrieval rates are continuing to increase at an alarming rate. At
future technology nodes, the time required to source manufacturing
problems must at least remain constant to maintain anticipated
productivity. Current commercial and manufacturer in-house data
management systems (DMS) have limited functionality in their ability to
access, analyse, and intelligently extract information from the large
variety of manufacturing data sources available within the
semiconductor manufacturing site. Write Comment (0 comments) |
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Feb 03, 2005 at 09:17 AM |
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PETER-M. HEINZE, Macrotron Systems GmbH, München, Germany ABSTRACT
A
defect detection tool utilising multiple beams at different wavelengths
has been developed and acquired a proven track record in wafer fab
utilities in Japan. The history of the development and the performance
of the tool is described and its advantages over the conventional
defect detector discussed. Write Comment (0 comments) |
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Feb 03, 2005 at 09:12 AM |
STEFAN SCHNEIDER, Forschungszentrum Jülich, Jülich, Germany
ABSTRACT
New materials for advanced memories device structures in multi-Gbit
DRAMs and FeRAMs are entering production. Managing the diversity of new
materials being introduced into the fab is a key technology. This
article covers the challenges for process and tool development to be
handled in dry etching of high-k materials. Write Comment (0 comments) |
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Feb 03, 2005 at 09:10 AM |
NOLAN KUAN, Applied Materials, Inc., Santa Clara, CA, USA
ABSTRACT
Today, in addition to technical drivers, there are strong economic
drivers in the semiconductor market for the use of single wafer thermal
processing tools, the primary driver being cycle time reduction.
Shorter product life cycles, decreasing technology adoption cycles, and
increasing time-to-market pressures require decreased development and
production cycle times. As semiconductor manufacturers transition from
200mm to 300mm wafers, they are choosing single-wafer toolsets to
deliver the technological and productivity benefits their products
demand.Write Comment (0 comments) |
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Feb 03, 2005 at 09:04 AM |
MICHAEL MAIDA, National Semiconductor GmbH, Fürstenfeldbruck, Germany
ABSTRACT
A new high speed analog device has been made. This article describes
the processes involved in obtaining the high performance and the
reasons for using such processing. The future of such devices is also
outlined.Write Comment (0 comments) |
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Feb 02, 2005 at 05:55 PM |
KENNETH ROSE & CHRISTOPHER MARK, Rensselaer Polytechnic Institute, Troy, NY, USA
ABSTRACT
As
CMOS chips are scaled to deep submicron dimensions, interconnects
increasingly limit performance. Achieving performance requirements can
lead to an explosion in the number of wiring levels required.
Alternative approaches to limiting long wire delay and reducing the
number of wiring levels are discussed. Tradeoffs in interconnect
strategies are compared.Write Comment (0 comments) |
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Feb 02, 2005 at 05:52 PM |
JAGDISH PRASAD & M. RAO YALAMANCHILI, SCP Global Technologies, Boise, ID, USA
ABSTRACT
In this paper we present results of the surface preparation processes
developed specifically to meet the ITRS requirements outlined for
particles, watermarks, surface roughness and metallic contamination.
These processes include a) a dilute SC1 process with integrated rinse
(termed "SC1 Pro-Rinse") for improved surface roughness and particle
removal and b) a drying process (termed "GreenDry") with integrated
chemical injection and rinse steps for watermark free final rinsing and
drying. Results from these new surface preparation processes clearly
indicate that these new technologies not only meet ITRS requirements
but also help reduce ESH impact by reduction in DI water consumption.Write Comment (0 comments) |
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Feb 02, 2005 at 05:50 PM |
MIKHAIL R. BAKLANOV & KONSTANTIN P. MOGILNIKOV, XPEQT, Tessenderlo, Belgium
ABSTRACT
Ellipsometric porosimetry (EP) is an effective method for
characterisation of porosity, pore size distribution (PSD) and specific
surface area in porous Low-K films. The films can be deposited on top
of any smooth substrate. EP is a new modification of the adsorption
porosimetry. In situ ellipsometry is used to determine the amount of
adsorptive which adsorbed/condensed in the film. Change in refractive
index is used to calculate of the quantity of adsorptive present in the
film.Write Comment (0 comments) |
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Feb 02, 2005 at 05:48 PM |
RAJIB AHMED, BRIAN SOPKO & JACOB JORNE, University of Rochester, Rochester, NY, USA
ABSTRACT
Methods of copper removal for microelectronics applications have been
explored. We have discussed the mechanisms of the more commonly
accepted chemical mechanical planarisation (CMP) processes. We also
have investigated the mechanisms of electrodissolution and
electropolishing. Two processes for improving the current methods of
dual damascene copper processing have been made.Write Comment (0 comments) |
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Feb 02, 2005 at 05:46 PM |
PETER BRATIN, GENE CHALYT & MICHAEL PAVLOV, ECI Technology, East Rutherford, NJ, USA
ABSTRACT
A new generation of online analysers of Damascene copper deposition
plating solutions based on cyclic voltammetric stripping (CVS) can
provide substantial yield improvements. The tight process window
typically required for void-free filing of submicrometre high aspect
ratio structures makes it important that additives be kept within a
tight range. This problem has been addressed by new online analytical
systems that sample plating tanks on a regular basis and determine the
rate at which chemicals in the plating tool need to be replenished.Write Comment (0 comments) |
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Feb 02, 2005 at 05:44 PM |
CHAD C. GARRETSON, JEFF P. RUDD, BRIAN J. BROWN, DAN FLYNN & STEVE CHEN, Applied Materials, Santa Clara, CA, USA
ABSTRACT
Pioneered by IBM in the 1980s, silicon dioxide was the first
application of chemical mechanical planarisation (CMP). As more
transistors are packed onto each chip, the number of interconnect
levels and the number of oxide CMP wafer passes has increased
dramatically. It is common today for 0.18-mm devices to require 5-8
oxide polishes for logic devices and 3-5 oxide polishes for DRAMs.
Oxide is today, and is likely to remain for several more years, the
largest CMP application. The biggest challenge to developing improved
oxide CMP process technology is achieving better process performance
with higher productivity and lower cost of ownership (CoO).Write Comment (0 comments) |
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Feb 02, 2005 at 05:41 PM |
KAREN MAEX, ZS. TOKEI, A. SATTA, F. LANCKMANS, W. WU & F. IACOPI, IMEC, Leuven, Belgium
ABSTRACT
The introduction of new dielectrics in the Back End of Line (BEOL)
processes is very challenging. The choice of the low k dielectric has a
large impact on all subsequent steps in the process, i.e. on the
deposition of hard masks, the patterning and strip process and the post
dry etch clean. The mechanical properties of the low k dielectric of
choice are directly related to the Cu deposition and the Cu CMP step.Write Comment (0 comments) |
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Feb 02, 2005 at 05:39 PM |
JILL C. HILDRETH, JEFFREY A. CHAN, ANDREW S. MORTON & HEATHER KRETZSCHMAR, Motorola Inc., Chandler, AZ, USA
ABSTRACT
To meet the high-frequency demands of today's wireless market, SiGe:C
heterojunction bipolar transistors have grown in popularity. This need
for speed has forced the novel process of SiGe:C epitaxy out of the
development laboratory and onto the factory floor. Not only must the
SiGe:C process meet device and product specifications, but to be cost
effective, it must include a process and tool monitoring plan that can
be executed around the clock by manufacturing personnel. Described
within is a methodology for manufacturing SiGe:C films with
industry-leading film quality using a reduced-pressure CVD reactor for
deposition. Use of this methodology has enabled Motorola to qualify
SiGe:C for production on a 0.35 µm BiCMOS platform.Write Comment (0 comments) |
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