LYNDON GRAHAM & TOM RITZDORF, Semitool, Kalispell, MT, USA
DAVE CLARKE, STEAG RTP Systems, San Jose, CA, USA
RANDHIR THAKUR, STEAG Electronic Systems, San Jose, CA, USA

Electrochemically deposited (ECD) copper films are studied for response to room temperature selfannealing and rapid thermal annealing (RTA) in a tungsten-halogen lamp based, rapid thermal processor. It is demonstrated that 1.3µm thick copper films with 0.25µm single damascene trench lines can be driven to recrystallise at a process temperature of 250ºC and time of 30 seconds as evidenced by post anneal grain growth. However, room temperature annealed (selfannealed) 0.25µm trenches did not fully recrystallise after one week although 0.75µm trenches and the bulk film has recrystallised.

YEZDI DORDI & PETER HEY, Applied Materials, Inc., Santa Clara, CA, USA

Copper electroplating has become the accepted process for depositing copper on semiconductor wafers. Achieving reliable via and trench filling is the principal challenge of the electroplating process, and this gap filling process is controlled by the kinetics of the copper plating reaction, which in turn is partially governed by the nature and concentration of trace amounts of organic additives in the electrolyte. Since additive concentrations are in the parts-per-million (ppm) range and are continuously depleted during the plating process as well as during system idle time, maintaining the correct electroplating bath composition is critical to achieving consistent void-free filling of vias, trenches and dual damascene structures.

JACOB JORNE, Cupricon Inc., Rochester, NY, USA

The main challenges facing the electroplating of copper on wafers for interconnection are uniformity and conformity. The difference between these two requirements is due to the scales involved. Uniformity over the entire wafer involves the scale of up to 30 cm, while the conformity and the filling ability of trenches and vias involve the scale of sub-micron. This difference requires clarification, as the traditional concept of throwing power is not applicable here. The non-uniformity of copper plating is due to the appreciable resistance of the thin barrier and seed layers and depends also on the geometry of the electroplating system

GREG HERDT, ALLEN MCTEER & SCOTT MEIKLE, Micron Technology, Inc., Boise, ID, USA

ABSTRACT

The transition from aluminium to copper interconnect technology is a key element of the current revolution in back-end of the line (BEOL) technology [1,2]. Considerations related to the implementation of PVD Cu barrier/seed processes are an integral part of this transition process. Development of manufacturable, cost-effective, and extendable PVD barrier/seed processes requires that integration with attendant BEOL processes be built-in from the start. This paperpresents some general issues that should be considered in developing PVD Cu barrier/seed processes that will be compatible with the requirements of the 0.15 µm generation and beyond.

TOM ROSENMAYER, JOHN BARTZ, SHICHUN QU & PING XU, W. L. Gore & Associates, Inc., Eau Claire, WI, USA

This article describes a potential dual-damascene etch process for an ultralow-k dielectric consisting of a nanocomposite of polytetrafluoroethylene (PTFE) and siloxane. PTFE has a high etch selectivity relative to common process materials. Trials of an integration scheme using this type of dielectric are described.

PETER SERMON, KNUT BEEKMANN AND SIMON MCCLATCHIE, Trikon Technologies Ltd., Newport, South Wales

New dielectric materials offering lower dielectric constants than silicon dioxide are needed for the manufacture of faster computer chips. In this article we survey the challenges involved in finding the right material.

PING XU & SUDHA S. RATHI, Applied Materials, Santa Clara, CA, USA

A low-k dielectric barrier/etch stop film, called BLOk™, has been developed for use in copper damascene processes. This silicon carbide film is deposited using trimethylsilane ((CH3)3SiH) and has a lower dielectric constant (k < 5) than that of conventional SiC films (k > 7) generated by SiH4 and CH4, and that of plasma silicon nitride (k > 7). Characterisation of the film, including physical, electrical, and copper diffusion barrier properties, and etch selectivity, shows that this film is a good barrier/etch stop for low-k copper damascene applications. Its low dielectric constant enables a significant reduction in the effective k value of the completed dielectric stack in damascene devices.

LUDO DEFERM, IMEC, Leuven, Belgium

The shift from aluminium to copper interconnect schemes in integrated circuits will eventually become a standard for 0.13 µm and even further scaled down CMOS processes. The introduction of Cu in 0.18 µm and larger technologies is only now taking place in some companies and for some applications, delayed largely by the problems of bringing new Curelated technologies into manufacturing. Eventually, copper combined with low-k dielectric materials using dualdamascene processing will replace standard aluminium interconnects in new technology generations.

MARCUS SCHUMACHER, JOHANNES LINDNER, PIOTR STRZYZEWSKI, MARTIN DAUELSBERG & HOLGER JUERGENSEN,
AIXTRON AG, Aachen, Germany

MOCVD processing of new materials such as perovskite type ceramic thin films will be one of the major key technologies for a new semiconductor device architecture in the field of ULSI non-volatile and volatile memory applications. This article outlines general trends and challenges in the field of MOCVD equipment and process development, driven not only by material performance aspects but especially by new integrated device applications like smart IC- and contactless RF-ID cards.

MATTHEW BANET, MICHAEL JOFFE, MICHAEL GOSTEIN, ALEX MAZNEV, ROBIN SACCO & FRANÇOISE QUEROMES,
Philips Analytical, Natick, MA, USA

The semiconductor industry is gradually replacing aluminium with copper as the metal of choice for interconnects in ICs. Copper interconnects are formed in a dual-Damascene structure that relies on chemical-mechanical polishing (CMP) to remove unwanted copper, leaving only a network of copper-filled Damascene trenches. Unfortunately, CMP of copper often leaves structures that have defects such as non-uniform thickness, rounding, dishing and erosion.

M. G. HEATON, L. M. GE* & F. M. SERRY, Digital Instruments, Veeco Metrology Group, Santa Barbara, CA, USA
*Currently at Intel Corp., Santa Clara, CA, USA

Chemical mechanical polishing (CMP) has become widely used in the semiconductor industry due to its ability to provide global planarisation for a wide range of sub-micron processes. With the widespread adoption of CMP and continually shrinking IC device dimensions, demands on metrology tools to characterise the process have also greatly increased. Higher resolution, higher performance, non-destructive metrology is now required to accurately and repeatably measure both large scale and fine-scale features using the same tool. To meet these needs, we have developed a new tool - the Atomic Force Profiler - that combines the benefits of profilometry and atomic force microscopy.

TOM HOGEL & LES MARSHALL, TRW Inc., Austin, TX, USA

Traditional capital equipment procurement practices in the semiconductor industry usually rely upon suppliers to deliver what they have promised in their quotation, with "automation" needs naturally appearing way down the list in terms of priorities. Actual tool automation capabilities and limitations are not "discovered" until the Equipment Interface (E.I.) characterisation phase, when there is little or no leverage available to coerce tool suppliers into correcting automation deficiencies.

SERN-IM LEE, IN-BO SIM & TODD C. WILLIAMS, COMPAQ Computer Corporation, Camas, WA, USA

Circuit designs and IC processing techniques become more complex every day. As a result the scope of manufacturing data required for analysis becomes larger and more critical. In order to handle the wealth of information, from a plethora of sources, many data warehousing concepts must be utilised. These include both data warehouses and data marts for all aspects of the manufacturing process. Sources of data for the circuit owner, quite often a Fabless entity, must include the wafer manufacturer, the IC manufacturer and the assembly shop. Currently all this information must also be fully Web-enabled. This allows the entire supply chain complete and confidential access to the information.
The concepts and requirements of a data mart are discussed in this article as well as some tools that assist in the data analysis process.

BRET W. ADAMS, BOGDAN SWEDEK, RAJEEV BAJAJ, FRITZ REDEKER, MANUSH BIRANG & GREGORY AMICO,
Applied Materials, Inc., Santa Clara, CA, USA

To achieve the benefits of using copper, users must minimise and control dishing and erosion across the wafer during the Cu CMP process. A new development in endpoint detection dramatically increases the detection sensitivity to when copper first clears by scanning across the full wafer diameter. This can be combined with a two-step polishing process to minimise dishing and erosion. Results of experiments using this system are described.

PETER BRATIN, GENE CHALYT, ALEX KOGAN, MICHAEL PAVLOV & JAMES PERPICH,
ECI Technology, Inc,. East Rutherford, NJ, USA

Use of electroplated copper for on-chip metallisation in semiconductor devices is gaining momentum because of low cost and high throughput of the process. Electroplated trenches and vias with submicron dimensions, however, are strongly affected by changes in the composition of the plating solution, thereby creating a high demand for control techniques. The most dynamic ingredients of electroplating solutions are organic additives.

THOMAS MEIDLINGER, Micronas GmbH, Freiburg, Germany
DANIEL R. MARX, Praxair MRC*, Orangeburg, NY, USA
JEAN-PIERRE BLANCHET, MRC SA, Toulouse, France

Enhancements to existing target designs developed by Praxair MRC are shown to generate significant reductions in cost of ownership in the PVD sputtering process. Tests at Micronas GmbH illustrate how a ring-enhanced aluminium alloy target provides a productivity gain both through increased erosion efficiency and through a 33% extension in target life while maintaining excellent uniformity. A 65% lifetime extension provided by recess-enhanced titanium targets provides a route to a reduction in Ti target consumption by 40%. The film quality met all requirements throughout the target lives.

ROBERT B. HIXSON, Integrated Device Technology, Hillsboro, OR, USA
PETER N. SWEETNAM, Semiconductor Equipment Technology, Inc., Dublin, CA, USA

Through the use of a parts management programme, Integrated Device Technology (IDT) has been able to reduce its equipment cost of ownership. The key aspects are: establishing an alternative source of parts; inspecting recycled parts to critical dimensions; tracking of recycled parts; pre-assembling kits where possible; custom-designing parts and surface finishes to address specific process requirements; and partnering with a supplier. While this article focuses on spare-parts management for physical vapour deposition (PVD), the approach is relevant to almost all other equipment sets as well.