Amal Chabli, CEA-Leti, Grenoble, France

ABSTRACT

Advanced interconnect integration for 45-nm nodes and below requires the use of copper metal lines and ultra low-k materials in order to control the delay, the crosstalk and the power consumption of the integrated circuits. This induces architecture specifications with introduction of new materials and new processes. Advanced physical and chemical characterization is mandatory to support not only the material choice and its improvement, the analysis of scaling effects and their correction, but also the design of integration processes and their validation. This article gives an overview of the most challenging characterization techniques in terms of their capabilities and limitations, giving special attention to sensitivity, localization and in-line metrology issues. 

Philippe Absil, Serge Biesemans, Jorge Kittl & Anne Lauwers, IMEC, Leuven, Belgium

ABSTRACT

With shrinking device technologies, industry is facing difficulty in reducing the oxide thickness to the required number as set by traditional scaling laws to maintain electrostatic integrity and sufficient drive current. The silicon MOSFET has entered the regime where further scaling of device parameters increases parasitic leakages, particularly the conduction through the gate dielectric. The use of a metal gate allows for scaling the electrical thickness without increasing this gate leakage. In this article, we silicided gates (FUSI) as a path to integrate materials with metal-like properties as gate electrodes on SiO₂ or high-k. A view on CMOS integration achieving proper Vts in both nMOS and pMOS is reviewed. 

Dr. Paul Ryan, Dr. Matthew Wormington & Helen Parnell, Bede X-ray Metrology, UK

ABSTRACT

With the move to 90nm technology nodes and beyond, manufacturers are looking at all stages of semiconductor fabrication to ensure that current process technologies are a match for increasingly demanding requirements. Metrology is no exception. 

Thomas P. Moffat & Daniel Josell, Materials Science and Engineering Laboratory, National Institute of Standards and Technology, Gaithersburg, MD, USA

ABSTRACT

The continuing drive for device miniaturization calls for further improvements in metallization performance and fabrication. Substitution of certain refractory metals such as Ruthenium or Osmium for conventional Tantalum barriers offers the prospect of improved thermal and electrical performance along with process simplification by permitting seedless Cu superfilling. Close attention to the surface state of the refractory metal surface is required in order to assure successful implementation. 

Axel Preusse, AMD Fab 36 LLC & Co. KG & Markus Nopper, AMD Saxony LLC & Co. KG, Dresden, Germany

ABSTRACT

Ever since copper plating together with the dual damascene integration scheme established itself as the mainstream, filling of via-holes and trenches has been the focus of interest for process engineers as well as integration experts. 

H. S. Rathore, D. B. Nguyen, B. Agarwala, K. Chanda, R. G. Filippi, D. Edelstein, C. C. Yang, A. Cowley, W. Landers, M. Yoon, L. Clevenger, J. Demarest, C. R. Davis & C. A. Barile, IBM Systems and Technology Group, Hopewell Junction, NY, USA; C. K. Hu, IBM T. J.Watson Research Center, Yorktown Heights, NY, USA, F. Chen, IBM Systems and Technology Group, Essex Junction, VT, USA, D. Hawken, IBM Systems and Technology Group, Endicott, NY, USA

ABSTRACT

IBM has implemented copper because of its higher conductivity and scalability, to allow lower capacitances at higher current densities than Al, and to proceed to smaller dimensions at better reliability. The performance can be further enhanced by integrating low-k dielectric with copper to decrease capacitive load and RC delay of interconnects. Here we report the reliability stress result of 90-nm copper interconnects with CVD low-k as BEOL dielectric. 

François Thomas, Field Marketing Director, Cadence Europe IC, Velizy, France

ABSTRACT

For some time, power has been a design issue, particularly with mobile applications where longer battery life is always desirable - wireless phones, Palm computers, laptop computers, etc. But as complexity and speed increase, all applications become power limited, especially in applications such as set-top boxes, DVD players/recorders and video games, which are mainly used in the family home where noisy fans are not acceptable. Even for computing or communication infrastructures, power dissipation has become a costly issue and a limitation. 

John Yamartino, Vivien Chang, James Holland & Andrey Poliektov, Applied Materials, Inc., Santa Clara, CA, USA

ABSTRACT

Device scaling is posing new challenges for many aspects of semiconductor processing. More sophisticated and flexible advanced process controls (APC) are needed for sub-90-nm applications to overcome limitations inherent in techniques that have proven effective for larger nodes. Not only must next-generation process-tool-based APC systems be able to receive metrology data from more than one source and translate them into process-control parameters to reduce performance variations, they must provide the fab host with features for designating the entire process control sequence for wafers passing through the system. Such APC systems will give fabs the highly desirable versatility needed for tailoring APC implementation to best advantage for its particular production lines. 

R. SINGH, V. PARIHAR, K. F. POOLE, Clemson University, Clemson, SC, USA
K. RAJKANAN, KLA- Tencor Corporation, Miltipas, CA, USA

Continued reduction of feature size, significant improvement in the functionality of new semiconductor products and simultaneously maintaining the historical rate of cost reduction of new products are the three most important challenges faced by the semiconductor industry in the 21st century. From a process integration point of view, the introduction of new materials (e.g. copper as conductor, as well as high and low k dielectrics) will be the most difficult challenge for semiconductor manufacturing in the 21st century. In a paradigm shift, understanding the role of defects and how they affect yield will be as important as the introduction of SPC was in leading to increased yield, some years ago.

GREG WILLITS & BRIAN FRASER, VERTEQ, Inc., Santa Ana, CA, USA

As CMP processing matures, the combined polisher and cleaner equipment set must achieve higher levels of performance and productivity. A new cleaning technology based on single-wafer megasonics is investigated for its ability to improve the productivity of CMP through elimination of brushes and the use of an embedded integration architecture.

FRANCES MARKEL, MATTHEW SIMPSON, OH-HUN KWON & MARC ABOUAF
Saint-Gobain Industrial Ceramics, Inc., Northboro, MA, USA

Recent advances in ceramic materials and processing technologies have enabled manufacturers of ceramics to overcome critical problems of contamination control. These advances also enable efficient thermal and mechanical designs, as well as appropriate electrical and optical properties for future semiconductor processing. This article summarizes the benefits provided by the properties of ceramics and the ease of fabrication of ceramic components for the next generation of semiconductor processing.

WEI-JEN HSIA, WILBUR CATABAY, DUNG-CHING PERNG, & PETER J. WRIGHT, LSI Logic, Santa Clara, CA, USA
LIAM CUNNANE, KNUT BEEKMANN, SIMON MCCLATCHIE & ADRIAN KIERMASZ, Trikon Technologies Ltd, Newport, Gwent, UK

The approach to the integration of low-k materials studied in this article is to use an inorganic material such as silicon dioxide doped with organic components. Embedded and non-embedded integration schemes are described. Electrical data shows that the low-k material performs as well as or better than a standard oxide.

BEN PANG, WAI-FAN YAU, PETER LEE & MEHUL NAIK, Applied Materials Inc., Santa Clara, CA, USA

A low dielectric material, "Black Diamond", based on Silicon Dioxide has been developed. The density of the material and hence the dielectric constant can be modified by choosing an appropriate terminating molecular group. It has the added advantage that the properties of Silicon Dioxide are retained for the device manufacturing processes. It is produced by conventional CVD and so should be compatible with normal Fab line operations.

PETER M. ZEITZOFF, SEMATECH Inc., Austin, TX, USA

The 1997 version of the National Technology Roadmap for Semiconductors, (NTRS), ref [1], assumes the continuation of Moore's Law type scaling for mainstream CMOS technology for the next fifteen years. For the 180 through the 100 nm technology generations, key trends are continued sharp scaling of Vdd and device dimensions such as gate oxide thickness, junction depths, gate length, contact and metal layer minimum dimensions, etc., while the threshold voltage remains approximately constant.

KENTON D. CHILDS, STEPHEN P. CLOUGH & DENNIS F. PAUL, Physical Electronics, Eden Prairie, MN, USA

One of the major challenges for yield enhancement is the ability to accurately identify defects or particles; optical and SEM methods are insufficient. Compositional Metrology™, which provides the defect composition, can furnish the additional information needed. This technique uses Auger electron spectroscopy for compositional analysis. Results of the application of the technique to several defects are described.

V. K. F. CHIA, P. LINDLEY, & M. J. EDGELL, Charles Evans & Associates, Redwood City, CA, USA
S. BISWAS, Evans Europa, London, UK

Contamination introduced during semiconductor processing includes transition metals, mobile ions, carbon, and organics. These contaminants can be deposited onto the surface of the wafer or they can be energetically driven into the wafer, to depths of several nanometers. A host of analytical tools are available to measure these contaminants. Amongst these are magnetic sector SIMS (secondary ion mass spectrometry), quadruple SIMS, Surface SIMS (oxygen leak with magnetic sector SIMS), time-of-flight SIMS (TOFSIMS), total reflection x-ray fluorescence (TXRF), vapour phase decomposition TXRF (VPD-TXRF), and VPD-atomic absorption (VPD-AA).

MICHAEL J. DENT, Spectra International, Morgan Hill, CA, USA

The inexorable march toward wide scale use of insitu sensor control loops is already taking place. The rocketing cost of manufacturing mistakes in a modern production fab or foundry combined with larger wafers, and smaller line geometries, demands in-situ sensor measurement and control, in real time. The outdated reputation of poor reliability and applicability of these techniques is being replaced by a rapidly growing and more widespread sensor use, in many cases product is not made unless the in-situ sensors are reading "go"!

JOHN CONWAY, Schneider Electric, Raleigh, NC, USA
JEFF. SEWARD, IBM Microelectronics, Burlington, VT, USA

This paper discusses the implementation challenges encountered when integrating smart sensors with manufacturing equipment to detect processing faults and improve yield. To overcome these problems, reliable and industry-hardened solutions must be deployed which are based on an open architecture. Certain sensor-based solutions must be able to perform control functions in real-time (measured in milliseconds) and if necessary intervene to halt the manufacturing process independently of the Manufacturing Execution System (MES) and Advanced Process Control (APC) system.

FRANK WEILER, TERRY MA & DAVID CHEN, Avant! Corporation, Fremont, CA, USA

Fierce competition in the market forces new generations of technologies to be rolled out every six to twelve months. In the 1990s, technology propels the success the pure-play foundries such as TSMC, UMC, and Chartered Semiconductor Manufacturing. They are the result of delivering very solid technologies to customers at very competitive prices.