Written by P. J. Timans & N. Acharya, Mattson Technology

ABSTRACT

Low-energy ion implantation can be combined with millisecond-duration annealing at temperatures just below the melting point of silicon to form very shallow junctions with a high degree of electrical activation. A prototype pulsed heating system based on a xenon flash lamp was used to study the annealing of low-energy B-implants in silicon. The sheet resistance and junction depth results suggest that this approach can meet the requirements for highly scaled MOS devices. Despite these encouraging results, millisecond annealing faces many difficult challenges before it can be implemented in volume manufacturing. The large temperature gradients and thermal stresses induced in the wafer by pulsed energy sources or scanned energy beams present formidable challenges for process control. 

Jane P. Chang & Lin Sha, Dept. of Chemical Engineering, University of California

ABSTRACT

The aggressive down-scaling of microelectronics devices into the nano-scale poses great challenges to plasma etching in patterning novel materials, such as high-k gate dielectrics. To design and optimize these chemically enhanced etching processes to better control the surface etching specificity and selectivity, it is crucial to understand two mechanisms that dictate the plasma-surface interactions: the ion energies with respect to the etching threshold energy and the addition of passivants. 

L. Broussous, P. Besson & O. Hinsinger, STM microelectronics amd T. Billon, CEA-Leti and S. Hemry & M. Frank SEZ AG

ABSTRACT

This work represents the investigation of the improvement of cleaning efficiency related to the use of the SEZ Spin Processor 203 in comparison to a static wet bench on Cu on SiOC and porous SiOC structures The focus was on postetch cleaning for 90-nm and 65-nm technology nodes with SiOC and porous SiOC dielectrics. A screening was performed to evaluate chemistries compatible with all the dielectrics involved in SiOC and porous SiOC integration. The chemicals were selected from previous experiments at Leti, [1] in collaboration with Crolles 1 R&D teams, as well as new propositions from chemical suppliers. Electrical and analytical data were used to evaluate the chemicals for post-etch cleaning of Cu and low-k. 

Arkadii Samoilov & Yihwan Kim, Applied Materials

ABSTRACT

Elevated source/drain epitaxial Si deposition (on bulk and SOI substrates) and recessed epitaxial SiGe ultra-shallow junction techniques for logic MOSFETs, elevated source/drain and contact plug fill integration schemes for DRAM, self-aligned deposition of the base and spacer of hetero-junction bipolar transistors - these methods are increasingly used by chip manufacturers to boost performance of semiconductor devices. Productionworthy, safe, reliable equipment and process solutions, with tight control of deposition results are required to support the industry's shift towards using selective epitaxy. 

M. Yang, L. Shi, K,#. Chan, E. Gusev, K. Jenkins, J. Ott, K. Guarini, C. D'Emic, M. Cobb, P. Moone, K. Rim, K Chan, F. Cardone, L. Tai, S. Koester, D. Canaperi,  B. To, E. Duch, I. Babich, R. Carruthers, P. Saunders, M. Steen, Y. Zhang, M. Leong, IBM Semiconductor R&D Canter, Research Division, USA and D. Boy, J. Ott, N. Klymko, G. Wlker, M. Ieong, V. Chan, A. Chou,  Y. Ninomiya, D. Pendelton, Y. Surpris, D. Heenan, N. Rovedo & H. Ng, IBM Microelectronic Division, Hopwell Junction, USA.

ABSTRACT

Methods to put strained silicon directly on an insulator layer and to produce CMOS structures with optimised silicon orientations are considered. Common to both enhancements is a technique to transfer layers using wafer bonding.  Indications of progress in producing devices on these special substrates and transistor characteristics are given. Potential for future scaling of devices is also investigated. 

A.H. Fischer, A. von Glasow, S. Penka & F. Ungar, Reliability Methodology, Infineon Technologies AG,
Munich, Germany

ABSTRACT

Electromigration (EM) and stressvoiding (SV) are critical wear-out mechanisms in copper metallizations, limiting the lifetime of complex interconnect systems [1–3]. As the trend goes to higher currents and operation temperatures, it is a great challenge for process integration to obtain highly reliable interconnects that are operable, e.g. at 6 mA/μm2 and 125°C for more than 10 y, tolerating only “few ppm” failures. The key to meet such targets is the optimization of single processes that yield appropriate microstructural properties of the copper and adequate interfaces along the liner or the cap layer. This paper will focus on process-related influences on the EM and SV behavior, where three categories are distinguished: Processes that influence local properties of the copper or liner at the via-to-line transition (I), that change the grain structure of copper (II), that change interface properties between Cu and cap layer (III).

Robert A. Binstead, Jeffrey M. Calvert & Robert Mikkola, Shipley Company, L.L.C., Marlborough, USA; Jonathan Reid & John Sukamto, Novellus Systems Inc., Tualatin, USA

ABSTRACT

The development of the copper damascene process by IBM has revolutionized the design and manufacture of advanced integrated circuits, allowing metal interconnects to shrink with each technology node while maintaining low-resistance wiring pathways. In combination with improvements in the interlayer dielectric materials, the use of copper interconnects has allowed chip designers to reduce the size of active transistor elements, and lower their operating voltage. This has resulted in an overall reduction in RC delay times, so producing smaller, faster devices with lower power requirements. In addition to improved device capabilities, each shrink in technology node has provided the opportunity to lower the cost of manufacture provided that acceptable yield and reliability can be maintained. The copper electroplating process is a key technology that has a significant impact on device yield, and the chemistries used to control the electrodeposition of copper interconnects have had to evolve to meet the stringent requirements of the semiconductor manufacturing processes. In this article we discuss some of the challenges for copper plating chemistries, and illustrate the improvements that have been realized in one of the contending chemistries intended for the sub-90nm node.

Drs. Wilbert G. M. van den Hoek, Chief Technical Officer and Executive Vice President of Integration and Advanced Development and CMP Business Group, Novellus Systems

ABSTRACT

Semiconductor devices have been steadily shrinking in size for over a quarter of a century. As a result, device speed is no longer determined by the transistor speed, but by the performance of the interconnect. To enable the continuation of device speed improvements, over the past five years the semiconductor industry has had to choose between two key new interconnect manufacturing technologies: copper interconnects, or low-k dielectric films. It chose to implement copper metallization first, because it was perceived to be the “easier” technology. Today, after two generations of devices with copper, we are still facing the low-k intermetal dielectric (IMD) challenge.

R. Singh, A. Venkateshan, & K. F. Poole, Holcombe Department of Electrical and Computer Engineering, Clemson University, Clemson, USA

ABSTRACT

In this article we describe the advantages of lamp-based RTP systems for thermal processing of Cu/low-k metallization at 65-nm nodes and beyond. The spectrum of incoherent light sources plays an important role in the design of RTP systems. As compared to furnace processing, mini-furnaces and resistive heater-based RTP systems, lamp-based RTP systems provide less process variation that leads to reduced cost of the design and improved performance, reliability, and yield of advanced semiconductor products.

R. Singh, A. Venkateshan, M. Fakhruddin & K. F. Poole, Center for Silicon Nanoelectronics, Clemson University and N. Balakrishnan & L. D. Fredendall, Dept. of Management, Clemson University

ABSTRACT

In this paper we have described the importance of single wafer processing (SWP) in semiconductor industry.. As compared to batch processing, reduced cycle time, reduced processing temperature, reduced process variation and reduced defect densities are some of the attractive features of SWP.