Dr. Paul Ryan, Bede X-Ray Metrology plc, Durham, England

ABSTRACT

Ever since Gordon Moore’s original prediction of how the number of transistors on a chip would increase over time [1], the key method of achieving this increase has been via scaling of the traditional CMOS transistor through improved lithography. By reducing the lateral dimensions, the density of devices can be increased. However, at the 90nm node, issues became evident that suggest that scaling alone would not be sufficient to keep pace with Moore’s law. Physical limits were being reached for the existing materials and it was clear that new materials and processes would have to be integrated into the transistors beyond the 90nm node to keep increasing the density and performance of chips. These new materials include SiGe, high-k/metal gates and porous dielectrics, and new processes - such as process-induced strain - require new metrologies for both development and increasingly to monitor the processes within production.

Dave Chapek, Semitool, Montana, USA

ABSTRACT

Front End Of Line (FEOL) surface preparation is about to grow up, and an entire industry is uncomfortable. The RCA clean is universally recognized as the reference standard in surface preparation.  It has been the core methodology for critical cleaning applications since it was introduced shortly after humanity first oxidized silicon and made planar MOS transistors.  Historically, the surface preparation unit process has demonstrated extraordinary power to disrupt factory operations and degrade product quality, risking incapacitation of the entire factory.  Subsequently, integrated device manufacturers have developed a virtually instinctive fear surrounding surface preparation, resulting in a daunting barrier to change.  We have all been grateful for the intrinsic elegance and functionality of the deceptively simple RCA chemical sequence that has served the industry for decades.
However, the twin forces of change at the heart of Moore’s Law, technology and productivity, are now revealing the limitations of the RCA sequence that has been an essential part of wafer fab operations.  As has been pointed out many times by many people of great accomplishment, we find ourselves facing the necessity of changing the very essence of the batch RCA cleaning sequence from an equipment perspective as processes push into the deep sub-50nm technology realm.
The question is:  What does that mean?

Uwe Seifert & Carlos Mata, Qimonda AG, Dresden, Germany; Thomas Trautzsch & Martin Tuckermann, KLA-Tencor GmbH, Dresden, Germany; Aneesh Khullar, Jorge Fernandez & Catherine Perry-Sullivan, KLA-Tencor Corporation, California, USA

ABSTRACT

Defect monitoring plays a critical role in the drive to obtain high yield and fast ramp in advanced memory device fabrication. However, in order to maintain cost effectiveness and operational efficiency, inspectors implemented as part of a yield strategy must adapt to changing inspection requirements, and detect defects on numerous devices, varying materials and multiple technology nodes. Broadband DUV inspection capability was introduced to Qimonda’s Defect Density Group, making it possible to collect broadband brightfield inspection data on several memory layers covering multiple materials and design rules. These data demonstrate that the process materials, pattern geometries and design rules all affect the optical contrast of defects of interest and nuisance events. These data further show that a brightfield inspector with a tunable broadband illumination source, selectable optical apertures, and advanced defect binning capability, provides the flexibility required to solve varying memory defectivity issues and to meet changing yield monitoring requirements. 

R. Arghavani, A. M. Noori, A. Gelatos, A. Khandelwal, S. Gandikota & S. Felch, Applied Materials, California, USA, & S. E. Thompson, University of Florida, USA

ABSTRACT

Significant breakthroughs in tool set, process and integration development have enabled implementing ~2 GPa of channel strain at the 45nm technology node.  High stress dielectrics (>2 GPa) are routinely used in several steps in the high-volume manufacturing process flows to introduce uniaxial compressive and tensile stress in the channel of MOSFETs.  The stress films are used for shallow trench isolation, contact etch stop, pre-metal dielectrics, removable films for stress memorization techniques, spacers and even salicidation.  Epitaxial silicon germanium in the source and drain (S/D) of p-MOSFETs is also adopted in high volume manufacturing resulting in a significant boost to p-channel performance.  Current innovative material processing appears to transfer enough stress to the channel to increase electron and hole mobility and meet 32nm and 22nm node logic performance goals.  However, there are significant signs that this improved mobility gain will not transfer into enhanced device performance due to parasitic external resistances becoming a bottleneck.  Such external resistances arise from junction, salicidation and contact processing.  Thus, a paradigm shift in device scaling is occurring at the 32nm technology node.  In this brief, we quantify the external resistance problem and offer possible solutions so that the full benefits of strain engineering are realized. 

M. Mellier, T. Berger, R. Duru, O. Hinsinger & G. Wyborn, STMicroelectronics, France; M. Rivoire, CEA–LETI, France & K-L. Chang, Y. Wang, V. Ripoche, S. Tsai & M. Thothadri, Applied Materials, USA

ABSTRACT

With the most advanced generation of integrated circuits using the integration of copper and fragile low-k or ultra low-k (ULK) dielectrics in Cu interconnects, the constraints on Cu chemical mechanical polishing (CMP) have become critical. There has been a great effort made to develop Cu CMP processes at lower pressures with improved topography behaviors to reduce sheet resistance (Rs) variations and to meet the stringent designs rules and compatibility with the lithography budget for depth of focus (DOF). 

Michael Gostein, John Byrnes, Alex Mazurenko & Tony Bonanno, Advanced Metrology Systems; Peter Weidner & Alexander Kasic, Qimonda Dresden, Germany; Philip Abromitis, Qimonda Richmond, USA

ABSTRACT

An important metrology challenge in the high-volume manufacturing of deep trench DRAM devices is the measurement of recess structures, formed in the poly fill near the top of the deep trench. These recesses are used to form final elements of the DRAM capacitor structure. For the shallow poly recess 2 and recess 3 structures, which are less than 300nm deep, AFM has until recently been the primary metrology method. However, infrared optical metrology is an increasingly attractive alternative because it provides higher throughput and better scalability to smaller critical dimensions. In this article we address the application of infrared metrology to these shallow recess structures for 90nm and 75nm trench DRAM, and discuss the potential benefits for future technology nodes.

Zsolt Tökei, Mikhail Baklanov, Ivan Ciofi, Yunlong Li & Adam Urbanowicz, IMEC, Leuven, Belgium

ABSTRACT

Porous low-k materials are required as interlayer dielectrics in future technology nodes in order to compensate for the RC-delay and power consumption increase associated with continuing device shrinkage. Porous low-k films are typically composed of silica and silsesquioxanes containing organic hydrophobic groups. The exposure of such films to a plasma ambient leads to an unwanted increase of the leakage current and of the dielectric constant of the film. The fundamentals of plasma damage, including low-k material modification and moisture adsorption, are explained and potential ways of reducing plasma damage are discussed. 

By Dr. Jagdish Prasad, AMI Semiconductor

ABSTRACT

As the physical and electrical limits of SiO₂ are approached, new materials and device architectures will be introduced to ensure adherence to Moore’s curve. These new materials and device architectures will most likely be introduced at 45nm and will continue to 32nm and beyond. Ni-based fully silicided (Ni-FUSI) with HfSiON CMOS shows promise at 45nm, while new architectures such as FinFET at 32nm will also be used. Introduction of high-k gate dielectric and metal gates will change the wafer cleaning process dramatically. Conventional RCA clean that contains hydrogen peroxide (H₂O₂) as one of the three components may no longer be used since hydrogen peroxide is known to dissolve metals, thus making it unsuitable for metal gates. The RCA process chemistry has many advantages such as excellent particle and metal removal capabilities. These advantages of RCA clean will be lost and will pose new challenges. Furthermore, drying high aspect ratio (>30:1) will be a challenge. Achieving complete drying of these challenging high aspect ratio structures at 45nm and beyond will require interface engineering. 

By Dr. Mike Cooke 

 ABSTRACT

The fast rise of Flash memory has been driven by the explosion of storage needs for mobile electronic devices such as phones, mp3 players, digital video and still cameras, personal digital assistants, etc. The Flash memory market has become so established that it has begun showing the fluctuations that are so familiar, and loathed, in the dynamic random access (DRAM) sector. Here we look at roadblocks for Flash’s further development and consider alternatives, particularly the phase-change memory that is considered by many to have more scaling potential.

By Victor Vartanian, Dina Triyoso, Kurt Junker, Mark Raymond, Michael Canonico, Greg Spencer, Marc Rossow, Stefan Zollner, Darrell Roan, James Smith and Chris Happ, Freescale Semiconductor, Inc., Texas, USA

ABSTRACT

The introduction of new materials associated with strained Si substrates such as SiGe, Ge, and III-V materials for enhanced carrier mobility has imposed new metrology challenges and techniques.  Both well-established techniques and others of more recent emergence are being used to address these challenges.  X-ray metrology has attained a prominent status in future thin film metrology applications.  Although the application of strained Si to conventional MOSFET devices is compatible with existing mainstream CMOS process technology, there are wafer quality monitoring demands and stringent requirements for film morphology and strain uniformity, imposing new demands in material characterization...(more)

By John West, VLSI Research, UK

ABSTRACT

The advent of integrated metrology (IM) has been a topic of interest for some time.  Back in the late 1990s, the predictions were that, at 100nm and beyond, integrated metrology would be indispensable for a wide range of semiconductor manufacturing processes. But the reality has been a rather different story, one in which vendors have had to battle against basic economics and standalone metrology to make relatively minor inroads into the metrology market.

Reza Arghavani, Hichem M'Saad, Ellie Yieh, Gary Miner & Satheesh Kuppurao, Applied Materials, California, & Scott E. Thompson, University of Florida

ABSTRACT

Historical device scaling has relied on gate length, gate dielectric and junction depth scaling to enhance performance. However, these conventional methods for device scaling have reached limits at the 90nm technology node with gate dielectrics being five atomic layers and junction depths being at ~10nm. Further scaling of either is not practical due to increased gate leakage currents or external resistance. Extrapolation of existing device trends shows significant barriers beyond the 45nm technology node. As a result, some semiconductor researchers have concluded that disruptive technologies such as vertical-transistor FinFETs or other exotic transistor architectures are required to achieve high-volume manufacturing at the 32nm node. 

Eric K. Lin, Wen-li Wu, Ronald L. Jones & Chengqing Wang, NIST, USA, Kwang-Woo Choi, George M. Thompson & Bryan J. Rice, Intel Corp., USA

ABSTRACT

While enormous effort has been expended in developing the optical lithography tools to print ever-finer features, significant advances have also been required to measure the shape and dimensions of the printed features. Currently, scanning electron microscopy and optical scatterometry methods are the primary metrology tools for gate stack, source-drain via, and interconnect metrology. Atomic force microscopy is used in special situations because of its ability to extract unambiguous three-dimensional information. 

Peter Weidner, Alexander Kasic, Thomas Hingst & Thomas Lindner, Qimonda Dresden, Germany

ABSTRACT

The demand for new DRAM technologies with smaller ground rules leads to new challenges for inline metrology. This paper addresses inline monitoring of structural dimensions like depths and critical dimension (CD), excluding defect density monitoring and advanced process control techniques. Qimonda pursues the deep trench (DT) capacitor concept. A main module in DRAM manufacturing comprises DT etch, capacity enhancing steps, and the connection of the DT to the device. Interesting demands for metrology emerge with every new technology node. Focusing on 75nm DRAM technology, this paper will highlight key processes in the DT module. 

Judy Wang, Shing-Li Sung & Shawming Ma, Applied Materials, USA

ABSTRACT

Contact-hole distortion results from low mask selectivity and poor mask surface quality (roughness, striation, pitting, or pin holes) before or after etching.  Thinner, softer ArF resists are particularly susceptible to these defects, giving rise to the need for additional steps in the etch sequence to mitigate pattern deformation.  Experimentation with a polymer deposition process shows that by adding this step before, after or before and after the bottom anti-reflective coat (BARC) open step, mask quality is much improved and contact profiles can be well controlled. 

Paul W. Mertens, Guy Vereecke & Rita Vos, IMEC, Leuven, Belgium

ABSTRACT

Removal of photoresist (PR) and residues is becoming very critical in future generations of devices.  In front-end-of-line (FEOL) post ion implantation (source/drain, extensions, halos, deep wells), the use of PR to block off parts of the circuit results in PR which is substantially hardened and difficult to remove.  In back-end-of-line (BEOL) etching, the selectivity to removing resist and residues without removing low-k materials is very challenging.  An overview of the status, issues and some novel approaches are presented. 

D. Lenoble, ST Microelectronics, Crolles, France

ABSTRACT

Based on calibrated - model simulations, this paper firstly highlights the significant impact of ultra-shallow junctions (USJ) in nano-scaled CMOS technologies. The specific  requirements of USJs according to the transistor's operating electrical targets are discussed and a dedicated figure of merit for USJs is proposed for assessing the applicability of published USJ formation processes. The integration issues are also presented from the point of view of circuit performance and manufacturability, including some economic analysis. Lastly, some perspectives on emerging doping processes are given and the main conclusions are summarized. 

R. Singh, P. Chandran, M. Grujicic, K.F.Poole, U. Vingnani, S.R. Ganapathi, A. Swaminathan, P.Jagannathan, & H. Iyer, Clemson University, South Carolina, USA

ABSTRACT

The 2005 International Technology Roadmap for Semiconductors (ITRS) has anticipated practical limits to complimentary metal-oxide- silicon (CMOS) scaling and expects the limit will be reached by 2020 with the 14nm technology node. Thus, there is an open question about the future of semiconductor manufacturing beyond the roadmap. With the emergence of the buzz word ‘nano technology', there are all kinds of speculations about some new semiconductor technology that will replace CMOS semiconductor manufacturing. In this paper, we have presented the fundamental requirements that are essential for any device to replace Si CMOS technology. An examination of the currently explored technologies to replace Si CMOS shows that most of these technologies have fundamental flaws. The ‘bottom up' approach of nanotechnology has fundamental limits of throughput and defects. As a result, the ‘top down' approach of CMOS manufacturing will continue to dominate electronics manufacturing beyond 2020. 

Dr P.H. Haumesser, Dr S. Maîtrejean & A. Roule, CEA-LETI, Grenoble, France; Dr G. Passemard, STMicroelectronics, Crolles Cedex, France

ABSTRACT

The damascene approach is now well established for the fabrication of advanced copper interconnects. However, as ultralarge integration progresses, process evolutions are mandatory to face the new challenges raised by feature size reduction. In this article, the extendibility of the copper deposition processes at the 32nm node is discussed. The PVD techniques used to grow the diffusion barriers and copper seed will probably have to be replaced by conformal processes. If ALD seems to be a promising solution for barrier deposition, the fabrication of an ultrathin and conformal seed layer is extremely challenging. Several solutions are examined and discussed. For feature filling, electrodeposition will probably remain the standard technique. However, the extension of existing solutions is challenging. What will be the metallization scheme at the 32nm node? This is surely an open question. Two main requirements will guide the selection of a process: the control of the copper/barrier interface, and most importantly the limitation of resistivity increase in the narrow lines.

D. Martin Knotter, Philips Semiconductors, Nijmegen, The Netherlands, & Jagdish Prasad, AMI Semiconductor, Pocatello, Idaho, USA

ABSTRACT

As new materials are introduced in semiconductor manufacturing at future technology nodes, new substrate cleaning processes are needed to meet the contamination requirements posed by ever shrinking geometries. Substrate cleaning requirements usually involve surface contamination such as micro-roughness, particles, metals and watermarks. The cleaning process usually varies with the substrate being cleaned. Therefore, it is very helpful to the manufacturing engineers to have cleaning processes for various substrates used in the semiconductor industry in one place as a reference. It is also important to understand the fundamental principles of cleaning and drying and therefore, in this paper we also present the basic principles of these processes. We have compiled the information on the cleaning processes used for various substrates in the semiconductor industry. The purpose of this article is to serve as a reference document on cleaning processes and chemistries used for various substrates in semiconductor manufacturing.