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Feb 02, 2005 at 04:13 PM |
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BRUNO GEOFFRION, ANJANA PATEL, STEVE KIM, MUHAMED RASHEED, NAREN
DUBEY, KEN LAI, JOE D'SOUZA, PADDY KRISHNARAJ & MANOJ VELLAIKAL,
Applied Materials, Santa Clara, CA, USA ABSTRACT
Anew 300 mm HDP-CVD
process has been designed to meet the requirements of the 0.10 µm
technology node and below. Processes have been developed for shallow
trench isolation (STI), pre-metal dielectric (PMD) and inter-metal
dielectric (IMD) gap filling that meet 0.10 µm technology node
requirements. This article examines the HDP-CVD process improvements
and their impact on gap fill and productivity at sub-0.10 µm with
aspect ratios greater than 6:1. Write Comment (0 comments) |
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Feb 02, 2005 at 04:09 PM |
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STEVE LASSIG, SIMON MCCLATCHIE & ADRIAN KIERMASZ, Lam Research Corporation, Fremont, CA, USA ABSTRACT
Materials
and processes for the back end of the line (BEoL) are changing.
Shrinking design rules have continued to increase the number of
interconnect layers required. Strategies to minimise interconnect
delays involve improving conductivity with copper wiring and lowering
the dielectric constant (k) value by employing low k films. While
copper integration is fairly advanced, low k materials present a wide
range of new integration challenges because of their lower density,
inferior mechanical properties, and typically increased organic
content.Write Comment (0 comments) |
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Feb 02, 2005 at 04:06 PM |
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MEGGY GOTUACO, PETER W. LEE, LI-QUN XIA & ELLIE YIEH, Applied Materials, Santa Clara, CA, USA ABSTRACT
As
chip manufacturers prepare to implement advanced copper and low K
interconnects, debate continues over chemical vapour deposition (CVD)
versus spin on dielectric (SOD) low-K approaches. Key challenges to
low-K implementation include resist compatibility and selectivity,
resistance to plasma attack during etching and photoresist removal,
adequate adhesion and strength to withstand CMP, wire bonding and
packaging, and overall device reliability. As chipmakers start putting
these films into production, the additional requirements of cost of
ownership and extendibility to the ≤100-nm generation also come into
play. This article presents research data that substantiates the
viability of a CVD low-K film for the production of <0.13-µm devices.Write Comment (0 comments) |
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Feb 02, 2005 at 04:04 PM |
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ANANTHA SETHURAMAN, SAGAR A. KEKARE, RAMAN NURANI & DADI GUDMUNDSSON, KLA-Tencor Inc., San Jose, CA, USA ABSTRACT
The
move to a smaller design rule and the associated processing methods are
automatic by-products of the demand for ever more powerful ICs. As a
result, there are some anticipated yield management challenges.
Coinciding with the most recent IC design rule reduction is the
long-awaited transition to 300 mm processing, which presents several
unique yield management problems not emphasised before. Some of the
process control and defect inspection methodology challenges associated
with the 300 mm transition are summarised, and the fundamentals of
surmounting them are discussed. Key conclusions are the potential
emergence of new defect inspection points and the importance of
including yield management in the fab planning process from the
beginning. Write Comment (0 comments) |
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Feb 02, 2005 at 04:02 PM |
JAN WILLIS, Simplex Solutions, Mountain View, CA, USA
ABSTRACT
In
recent years, the complexity of chip interconnect has become one of the
most significant gating factors affecting chip design and performance.
The minuscule wiring that connects the millions of transistors on
advanced semiconductors can be thought of as the "freeway system" of
the chip. Through these submicroscopic connections, electrical signals
flow to the complex network of transistors and diodes that have been
painstakingly imprinted into the layers of silicon. This article
describes a new approach to chip interconnects.Write Comment (0 comments) |
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Feb 02, 2005 at 03:59 PM |
DANIELE CONTESTABLE-GILKES, SAILESH M. MERCHANT & MINSEOK OH, Agere Systems, Orlando, FL, USA
ABSTRACT
Increased device speed and improved electromigration are two main
drivers for the semiconductor industry's transition from aluminium to
copper for integrated circuit interconnects. A major disadvantage of
copper is its fast diffusion rate into underlying substrates.
Therefore, in order to benefit from the advantages of lower sheet
resistance and improved electromigration by using copper, a
high-quality, high-performance diffusion barrier is also necessary.
Various transition and refractory metals, their alloys, silicides and
nitrides, such as Ta and TaNx, prevent copper from diffusing into
adjacent dielectrics.Write Comment (0 comments) |
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Feb 02, 2005 at 03:54 PM |
SHIVA RAMACHANDRAN, Clarkson University, Potsdam, NY, USA
AHMED A. BUSNAINA, Northeastern University, Boston, MA, USA
ROBERT SMALL & CASS SHANG, EKC Technology, Hayward, CA, USA
ABSTRACT
In
this article, an investigation of brush cleaning of post-CMP wafers
using a chelating basic chemistry is presented. Silica slurry particles
were deposited on the wafer surface by dipping. The effect of brush
speed, pressure and cleaning time on cleaning is described. The
cleaning efficiency was found to be near 100% over most of the range of
parameters investigated.Write Comment (0 comments) |
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Feb 02, 2005 at 03:50 PM |
MARIA PETERSON & KATHLEEN PERRY, Cabot Microelectronics Corporation, Aurora, IL, USA
ABSTRACT
Device shrinks continue to drive more stringent performance
requirements for every step of IC manufacturing. Increased numbers of
metal layers and smaller critical dimensions demand even more planar
surfaces than were previously acceptable. New materials being
introduced - low-k dielectrics, high-k dielectrics, noble metals -
require creative chemical and mechanical approaches to planarisation
that enable multiple integration strategies.Write Comment (0 comments) |
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Jan 21, 2005 at 10:45 AM |
P.A. Kraus, C.S. Olsen, K. Ahmed, T.C. Chua, R. Zhao, F. Nouri, & J. Cushing, Front End Products Group, Applied Materials, Inc., Santa Clara, CA, USA
ABSTRACT
Many technical and manufacturing challenges exist
for scaling gate oxide dielectrics to 65 nm. Plasma nitridation of the
gate oxide has demonstrated advantages in nitrogen dose and profile
control over other nitridation methods. Improvements in the
plasmanitridation process have been developed that result in improved
device performance, including reduced threshold voltage shifts, reduced
mobility degradation, and improved reliability. Clustering the gate
oxidation, nitridation, post nitridation anneal, and poly deposition
has also been demonstrated to reduce EOT, improve within wafer EOT
uniformity, and enhance drive current over non-clustered processing.
These improvements lead to scaling the plasma nitridation process to
the 65-nm technology node.Write Comment (0 comments) |
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Jan 20, 2005 at 10:53 AM |
Lionel Girardie, MEMSCAP SA, Crolles, France et al
ABSTRACT
Alternative dielectric materials replacing silicon
dioxide is proposed
by a new scheme of alloying films and interfaces. This scheme is based
on specific atomic layer deposition (ALD) process with laminated films
for MIM applications and with graded compound films for FET
applications.
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Wafer Processing 
Product Briefing Outline: Aviza Technology has launched the Versalis fxP, a 200/300mm cluster system targeted for 3D-IC manufacturing using through silicon via (TSV) technology. The Versalis fxP is based
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Product Briefing Outline: Lam Research has introduced the 2300 Versys Kiyo3x conductor etch series, which the company claims can achieve CD uniformity levels of 1nm across the wafer, a key
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Product Briefing Outline: Novellus Systems has launched two specific dry strip and clean systems that each target different photoresist removal requirements for leading-edge logic and memory manufacturing. The ‘G400’ is
Read More
The Wafer Processing section deals with both Front End of Line (FEOL)
and Back End of Line (BEOL) wafer processing issues for leading edge
CMOS work streams only. Articles are commissioned from experts in their
fields that include IC manufacturers, R&D centres, capital
equipment companies and Universities from around the world. 
