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Feb 02, 2005 at 05:55 PM |
KENNETH ROSE & CHRISTOPHER MARK, Rensselaer Polytechnic Institute, Troy, NY, USA
ABSTRACT
As
CMOS chips are scaled to deep submicron dimensions, interconnects
increasingly limit performance. Achieving performance requirements can
lead to an explosion in the number of wiring levels required.
Alternative approaches to limiting long wire delay and reducing the
number of wiring levels are discussed. Tradeoffs in interconnect
strategies are compared.Write Comment (0 comments) |
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Feb 02, 2005 at 05:52 PM |
JAGDISH PRASAD & M. RAO YALAMANCHILI, SCP Global Technologies, Boise, ID, USA
ABSTRACT
In this paper we present results of the surface preparation processes
developed specifically to meet the ITRS requirements outlined for
particles, watermarks, surface roughness and metallic contamination.
These processes include a) a dilute SC1 process with integrated rinse
(termed "SC1 Pro-Rinse") for improved surface roughness and particle
removal and b) a drying process (termed "GreenDry") with integrated
chemical injection and rinse steps for watermark free final rinsing and
drying. Results from these new surface preparation processes clearly
indicate that these new technologies not only meet ITRS requirements
but also help reduce ESH impact by reduction in DI water consumption.Write Comment (0 comments) |
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Feb 02, 2005 at 05:50 PM |
MIKHAIL R. BAKLANOV & KONSTANTIN P. MOGILNIKOV, XPEQT, Tessenderlo, Belgium
ABSTRACT
Ellipsometric porosimetry (EP) is an effective method for
characterisation of porosity, pore size distribution (PSD) and specific
surface area in porous Low-K films. The films can be deposited on top
of any smooth substrate. EP is a new modification of the adsorption
porosimetry. In situ ellipsometry is used to determine the amount of
adsorptive which adsorbed/condensed in the film. Change in refractive
index is used to calculate of the quantity of adsorptive present in the
film.Write Comment (0 comments) |
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Feb 02, 2005 at 05:48 PM |
RAJIB AHMED, BRIAN SOPKO & JACOB JORNE, University of Rochester, Rochester, NY, USA
ABSTRACT
Methods of copper removal for microelectronics applications have been
explored. We have discussed the mechanisms of the more commonly
accepted chemical mechanical planarisation (CMP) processes. We also
have investigated the mechanisms of electrodissolution and
electropolishing. Two processes for improving the current methods of
dual damascene copper processing have been made.Write Comment (0 comments) |
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Feb 02, 2005 at 05:46 PM |
PETER BRATIN, GENE CHALYT & MICHAEL PAVLOV, ECI Technology, East Rutherford, NJ, USA
ABSTRACT
A new generation of online analysers of Damascene copper deposition
plating solutions based on cyclic voltammetric stripping (CVS) can
provide substantial yield improvements. The tight process window
typically required for void-free filing of submicrometre high aspect
ratio structures makes it important that additives be kept within a
tight range. This problem has been addressed by new online analytical
systems that sample plating tanks on a regular basis and determine the
rate at which chemicals in the plating tool need to be replenished.Write Comment (0 comments) |
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Feb 02, 2005 at 05:44 PM |
CHAD C. GARRETSON, JEFF P. RUDD, BRIAN J. BROWN, DAN FLYNN & STEVE CHEN, Applied Materials, Santa Clara, CA, USA
ABSTRACT
Pioneered by IBM in the 1980s, silicon dioxide was the first
application of chemical mechanical planarisation (CMP). As more
transistors are packed onto each chip, the number of interconnect
levels and the number of oxide CMP wafer passes has increased
dramatically. It is common today for 0.18-mm devices to require 5-8
oxide polishes for logic devices and 3-5 oxide polishes for DRAMs.
Oxide is today, and is likely to remain for several more years, the
largest CMP application. The biggest challenge to developing improved
oxide CMP process technology is achieving better process performance
with higher productivity and lower cost of ownership (CoO).Write Comment (0 comments) |
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Feb 02, 2005 at 05:41 PM |
KAREN MAEX, ZS. TOKEI, A. SATTA, F. LANCKMANS, W. WU & F. IACOPI, IMEC, Leuven, Belgium
ABSTRACT
The introduction of new dielectrics in the Back End of Line (BEOL)
processes is very challenging. The choice of the low k dielectric has a
large impact on all subsequent steps in the process, i.e. on the
deposition of hard masks, the patterning and strip process and the post
dry etch clean. The mechanical properties of the low k dielectric of
choice are directly related to the Cu deposition and the Cu CMP step.Write Comment (0 comments) |
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Feb 02, 2005 at 05:39 PM |
JILL C. HILDRETH, JEFFREY A. CHAN, ANDREW S. MORTON & HEATHER KRETZSCHMAR, Motorola Inc., Chandler, AZ, USA
ABSTRACT
To meet the high-frequency demands of today's wireless market, SiGe:C
heterojunction bipolar transistors have grown in popularity. This need
for speed has forced the novel process of SiGe:C epitaxy out of the
development laboratory and onto the factory floor. Not only must the
SiGe:C process meet device and product specifications, but to be cost
effective, it must include a process and tool monitoring plan that can
be executed around the clock by manufacturing personnel. Described
within is a methodology for manufacturing SiGe:C films with
industry-leading film quality using a reduced-pressure CVD reactor for
deposition. Use of this methodology has enabled Motorola to qualify
SiGe:C for production on a 0.35 µm BiCMOS platform.Write Comment (0 comments) |
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Feb 02, 2005 at 04:25 PM |
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MARTIN EMRICH, MACROTRON Systems GmbH, Munich, Germany PAUL MILLER,
DOUG PRICE & CHARLES BOWERS, Eco-Snow Systems, Inc., Livermore, CA,
USA ABSTRACT
A "dry" carbon dioxide process has been investigated as a
replacement for conventional solvent and deionised-water spray
techniques for metal lift-off process steps. Results show that wafer
yield is improved as a result of reduced electrical degradation and
particle density. We also observe reductions in contact resistance
between the interconnect metal and ohmic metal layers of greater than
20%. Write Comment (0 comments) |
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Feb 02, 2005 at 04:23 PM |
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WOO SIK YOO & TAKASHI FUKADA, WaferMasters Inc, San Jose, CA,
USA RIU KOMATUBARA, Tokyo Electron Ltd, Tokyo, Japan JIRO YAMAMOTO, NEC
Hiroshima Ltd, Hiroshima, Japan ABSTRACT
Rapid thermal annealing (RTA) of
various implant species (11B+, 49BF2+, 31P+ and 75As+) in 200mm
diameter Si wafers was done using a single wafer furnace (SRTF) system
and a lamp-based rapid thermal processing (RTP) system under 1 atm N2
atmosphere. Implant energy was varied between 70keV and 50keV. Average
sheet resistance and its uniformity were measured after annealing under
various conditions. Very efficient and uniform electrical activation
across the wafer was observed in a wide range of annealing conditions.
An alternative implant annealing strategy against the "spike anneal"
was proposed based on experimental results. Write Comment (0 comments) |
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Wafer Processing 
Product Briefing Outline: Aviza Technology has launched the Versalis fxP, a 200/300mm cluster system targeted for 3D-IC manufacturing using through silicon via (TSV) technology. The Versalis fxP is based
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Product Briefing Outline: Lam Research has introduced the 2300 Versys Kiyo3x conductor etch series, which the company claims can achieve CD uniformity levels of 1nm across the wafer, a key
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Product Briefing Outline: Novellus Systems has launched two specific dry strip and clean systems that each target different photoresist removal requirements for leading-edge logic and memory manufacturing. The ‘G400’ is
Read More
The Wafer Processing section deals with both Front End of Line (FEOL)
and Back End of Line (BEOL) wafer processing issues for leading edge
CMOS work streams only. Articles are commissioned from experts in their
fields that include IC manufacturers, R&D centres, capital
equipment companies and Universities from around the world. 
