JOHN CONWAY, Schneider Electric, Raleigh, NC, USA
JEFF. SEWARD, IBM Microelectronics, Burlington, VT, USA

This paper discusses the implementation challenges encountered when integrating smart sensors with manufacturing equipment to detect processing faults and improve yield. To overcome these problems, reliable and industry-hardened solutions must be deployed which are based on an open architecture. Certain sensor-based solutions must be able to perform control functions in real-time (measured in milliseconds) and if necessary intervene to halt the manufacturing process independently of the Manufacturing Execution System (MES) and Advanced Process Control (APC) system.

FRANK WEILER, TERRY MA & DAVID CHEN, Avant! Corporation, Fremont, CA, USA

Fierce competition in the market forces new generations of technologies to be rolled out every six to twelve months. In the 1990s, technology propels the success the pure-play foundries such as TSMC, UMC, and Chartered Semiconductor Manufacturing. They are the result of delivering very solid technologies to customers at very competitive prices.

KATRINA MIKHAYLICHENKO & MIKE RAVKIN, Lam Research Corp., Fremont, CA, USA
DAVE STEIN & DALE HETHERINGTON, Sandia National Laboratory, Albuquerque, NM, USA

Lam Research and Sandia National Laboratory have conducted studies that compare the cleaning capabilities of non-contact megasonic cleaning with contact cleaning that uses brush scrubbing. We found that partially planarised features are far more difficult to clean than polished blanket dielectric or metal surfaces. Features with larger step heights and/or small horizontal dimensions may efficiently trap slurry and are, of course, difficult to clean. To investigate the effect of topography size and aspect ratio on the relative cleaning efficiency of spin-rinse-dry (SRD), megasonic, and brush scrubbing techniques, special masks with topography of variable size and aspect ratio were developed.

MARC MEURIS, SOPHIA ARNAUTS, INGRID CORNELISSEN, K. KENIS, M. LUX, STEFAN DEGENDT, PAUL MERTENS,
I. TEERLINCK, R. VOS, L. LOEWENSTEIN & M. M. HEYNS, IMEC, Leuven, Belgium
KLAUS WOLKE, STEAG Microtech, Pliezhauzen, Germany

This article describes an implementation of the IMEC Clean for pre-diffusion cleans in a CMOS process. To avoid metal contamination HCl is added to the dilute HF. This also ensures particle removal. The particle removal and metal removal efficiencies are compared with those of an RCA clean. The results of monitoring of particle levels over 18 months and Fe concentration over a year are presented. The cost of ownership is also compared with that of an RCA clean.

ERNST GAULHOFER & HEINZ OYRER, SEZ A.G, Austria
BING-YUE TSUI, National Chiao Tung University, Hsinchu, Taiwan

Wafer cleaning is the most frequently repeated process in semiconductor manufacturing and with an industry-wide move to copper interconnects, contamination control requirements are extremely critical. Interconnect delay begins to dominate overall device delay at 0.18µm, making lowresistance copper attractive and a highly reliable cleaning process becomes essential, especially considering the expense of frequent contamination monitoring. Successful integration requires stringent control of cross contamination from deposition equipment (PVD, CVD, and electroplating tools), CMP equipment, and all metrology tools shared by copper processed wafers

MARIA L. PETERSON, ROBERT J. SMALL, TUAN TRUONG & JOO-YUN LEE, EKC Technology, Inc., Hayward, CA, USA

Planarizing copper deposited inlays is not a simple problem to solve. The change in crystallite orientation within the infill affects the polishing uniformity and processing wafers from different sources can add to the problems. The various pitfalls are discussed and polishing techniques explained. By using two stage polishing processes with  careful control of the slurry chemistry and abrasive particle geometry, excellent surface flatness has been obtained.

LYNDON GRAHAM & TOM RITZDORF, Semitool, Kalispell, MT, USA
DAVE CLARKE, STEAG RTP Systems, San Jose, CA, USA
RANDHIR THAKUR, STEAG Electronic Systems, San Jose, CA, USA

Electrochemically deposited (ECD) copper films are studied for response to room temperature selfannealing and rapid thermal annealing (RTA) in a tungsten-halogen lamp based, rapid thermal processor. It is demonstrated that 1.3µm thick copper films with 0.25µm single damascene trench lines can be driven to recrystallise at a process temperature of 250ºC and time of 30 seconds as evidenced by post anneal grain growth. However, room temperature annealed (selfannealed) 0.25µm trenches did not fully recrystallise after one week although 0.75µm trenches and the bulk film has recrystallised.

YEZDI DORDI & PETER HEY, Applied Materials, Inc., Santa Clara, CA, USA

Copper electroplating has become the accepted process for depositing copper on semiconductor wafers. Achieving reliable via and trench filling is the principal challenge of the electroplating process, and this gap filling process is controlled by the kinetics of the copper plating reaction, which in turn is partially governed by the nature and concentration of trace amounts of organic additives in the electrolyte. Since additive concentrations are in the parts-per-million (ppm) range and are continuously depleted during the plating process as well as during system idle time, maintaining the correct electroplating bath composition is critical to achieving consistent void-free filling of vias, trenches and dual damascene structures.

JACOB JORNE, Cupricon Inc., Rochester, NY, USA

The main challenges facing the electroplating of copper on wafers for interconnection are uniformity and conformity. The difference between these two requirements is due to the scales involved. Uniformity over the entire wafer involves the scale of up to 30 cm, while the conformity and the filling ability of trenches and vias involve the scale of sub-micron. This difference requires clarification, as the traditional concept of throwing power is not applicable here. The non-uniformity of copper plating is due to the appreciable resistance of the thin barrier and seed layers and depends also on the geometry of the electroplating system

GREG HERDT, ALLEN MCTEER & SCOTT MEIKLE, Micron Technology, Inc., Boise, ID, USA

ABSTRACT

The transition from aluminium to copper interconnect technology is a key element of the current revolution in back-end of the line (BEOL) technology [1,2]. Considerations related to the implementation of PVD Cu barrier/seed processes are an integral part of this transition process. Development of manufacturable, cost-effective, and extendable PVD barrier/seed processes requires that integration with attendant BEOL processes be built-in from the start. This paperpresents some general issues that should be considered in developing PVD Cu barrier/seed processes that will be compatible with the requirements of the 0.15 µm generation and beyond.