Axel Preusse, AMD Fab 36 LLC & Co. KG & Markus Nopper, AMD Saxony LLC & Co. KG, Dresden, Germany

ABSTRACT

Ever since copper plating together with the dual damascene integration scheme established itself as the mainstream, filling of via-holes and trenches has been the focus of interest for process engineers as well as integration experts. 

H. S. Rathore, D. B. Nguyen, B. Agarwala, K. Chanda, R. G. Filippi, D. Edelstein, C. C. Yang, A. Cowley, W. Landers, M. Yoon, L. Clevenger, J. Demarest, C. R. Davis & C. A. Barile, IBM Systems and Technology Group, Hopewell Junction, NY, USA; C. K. Hu, IBM T. J.Watson Research Center, Yorktown Heights, NY, USA, F. Chen, IBM Systems and Technology Group, Essex Junction, VT, USA, D. Hawken, IBM Systems and Technology Group, Endicott, NY, USA

ABSTRACT

IBM has implemented copper because of its higher conductivity and scalability, to allow lower capacitances at higher current densities than Al, and to proceed to smaller dimensions at better reliability. The performance can be further enhanced by integrating low-k dielectric with copper to decrease capacitive load and RC delay of interconnects. Here we report the reliability stress result of 90-nm copper interconnects with CVD low-k as BEOL dielectric. 

François Thomas, Field Marketing Director, Cadence Europe IC, Velizy, France

ABSTRACT

For some time, power has been a design issue, particularly with mobile applications where longer battery life is always desirable - wireless phones, Palm computers, laptop computers, etc. But as complexity and speed increase, all applications become power limited, especially in applications such as set-top boxes, DVD players/recorders and video games, which are mainly used in the family home where noisy fans are not acceptable. Even for computing or communication infrastructures, power dissipation has become a costly issue and a limitation. 

John Yamartino, Vivien Chang, James Holland & Andrey Poliektov, Applied Materials, Inc., Santa Clara, CA, USA

ABSTRACT

Device scaling is posing new challenges for many aspects of semiconductor processing. More sophisticated and flexible advanced process controls (APC) are needed for sub-90-nm applications to overcome limitations inherent in techniques that have proven effective for larger nodes. Not only must next-generation process-tool-based APC systems be able to receive metrology data from more than one source and translate them into process-control parameters to reduce performance variations, they must provide the fab host with features for designating the entire process control sequence for wafers passing through the system. Such APC systems will give fabs the highly desirable versatility needed for tailoring APC implementation to best advantage for its particular production lines. 

R. SINGH, V. PARIHAR, K. F. POOLE, Clemson University, Clemson, SC, USA
K. RAJKANAN, KLA- Tencor Corporation, Miltipas, CA, USA

Continued reduction of feature size, significant improvement in the functionality of new semiconductor products and simultaneously maintaining the historical rate of cost reduction of new products are the three most important challenges faced by the semiconductor industry in the 21st century. From a process integration point of view, the introduction of new materials (e.g. copper as conductor, as well as high and low k dielectrics) will be the most difficult challenge for semiconductor manufacturing in the 21st century. In a paradigm shift, understanding the role of defects and how they affect yield will be as important as the introduction of SPC was in leading to increased yield, some years ago.

GREG WILLITS & BRIAN FRASER, VERTEQ, Inc., Santa Ana, CA, USA

As CMP processing matures, the combined polisher and cleaner equipment set must achieve higher levels of performance and productivity. A new cleaning technology based on single-wafer megasonics is investigated for its ability to improve the productivity of CMP through elimination of brushes and the use of an embedded integration architecture.

FRANCES MARKEL, MATTHEW SIMPSON, OH-HUN KWON & MARC ABOUAF
Saint-Gobain Industrial Ceramics, Inc., Northboro, MA, USA

Recent advances in ceramic materials and processing technologies have enabled manufacturers of ceramics to overcome critical problems of contamination control. These advances also enable efficient thermal and mechanical designs, as well as appropriate electrical and optical properties for future semiconductor processing. This article summarizes the benefits provided by the properties of ceramics and the ease of fabrication of ceramic components for the next generation of semiconductor processing.

WEI-JEN HSIA, WILBUR CATABAY, DUNG-CHING PERNG, & PETER J. WRIGHT, LSI Logic, Santa Clara, CA, USA
LIAM CUNNANE, KNUT BEEKMANN, SIMON MCCLATCHIE & ADRIAN KIERMASZ, Trikon Technologies Ltd, Newport, Gwent, UK

The approach to the integration of low-k materials studied in this article is to use an inorganic material such as silicon dioxide doped with organic components. Embedded and non-embedded integration schemes are described. Electrical data shows that the low-k material performs as well as or better than a standard oxide.

BEN PANG, WAI-FAN YAU, PETER LEE & MEHUL NAIK, Applied Materials Inc., Santa Clara, CA, USA

A low dielectric material, "Black Diamond", based on Silicon Dioxide has been developed. The density of the material and hence the dielectric constant can be modified by choosing an appropriate terminating molecular group. It has the added advantage that the properties of Silicon Dioxide are retained for the device manufacturing processes. It is produced by conventional CVD and so should be compatible with normal Fab line operations.