Judy Wang, Shing-Li Sung & Shawming Ma, Applied Materials, USA

ABSTRACT

Contact-hole distortion results from low mask selectivity and poor mask surface quality (roughness, striation, pitting, or pin holes) before or after etching.  Thinner, softer ArF resists are particularly susceptible to these defects, giving rise to the need for additional steps in the etch sequence to mitigate pattern deformation.  Experimentation with a polymer deposition process shows that by adding this step before, after or before and after the bottom anti-reflective coat (BARC) open step, mask quality is much improved and contact profiles can be well controlled. 

Paul W. Mertens, Guy Vereecke & Rita Vos, IMEC, Leuven, Belgium

ABSTRACT

Removal of photoresist (PR) and residues is becoming very critical in future generations of devices.  In front-end-of-line (FEOL) post ion implantation (source/drain, extensions, halos, deep wells), the use of PR to block off parts of the circuit results in PR which is substantially hardened and difficult to remove.  In back-end-of-line (BEOL) etching, the selectivity to removing resist and residues without removing low-k materials is very challenging.  An overview of the status, issues and some novel approaches are presented. 

D. Lenoble, ST Microelectronics, Crolles, France

ABSTRACT

Based on calibrated - model simulations, this paper firstly highlights the significant impact of ultra-shallow junctions (USJ) in nano-scaled CMOS technologies. The specific  requirements of USJs according to the transistor's operating electrical targets are discussed and a dedicated figure of merit for USJs is proposed for assessing the applicability of published USJ formation processes. The integration issues are also presented from the point of view of circuit performance and manufacturability, including some economic analysis. Lastly, some perspectives on emerging doping processes are given and the main conclusions are summarized. 

R. Singh, P. Chandran, M. Grujicic, K.F.Poole, U. Vingnani, S.R. Ganapathi, A. Swaminathan, P.Jagannathan, & H. Iyer, Clemson University, South Carolina, USA

ABSTRACT

The 2005 International Technology Roadmap for Semiconductors (ITRS) has anticipated practical limits to complimentary metal-oxide- silicon (CMOS) scaling and expects the limit will be reached by 2020 with the 14nm technology node. Thus, there is an open question about the future of semiconductor manufacturing beyond the roadmap. With the emergence of the buzz word ‘nano technology', there are all kinds of speculations about some new semiconductor technology that will replace CMOS semiconductor manufacturing. In this paper, we have presented the fundamental requirements that are essential for any device to replace Si CMOS technology. An examination of the currently explored technologies to replace Si CMOS shows that most of these technologies have fundamental flaws. The ‘bottom up' approach of nanotechnology has fundamental limits of throughput and defects. As a result, the ‘top down' approach of CMOS manufacturing will continue to dominate electronics manufacturing beyond 2020. 

Dr P.H. Haumesser, Dr S. Maîtrejean & A. Roule, CEA-LETI, Grenoble, France; Dr G. Passemard, STMicroelectronics, Crolles Cedex, France

ABSTRACT

The damascene approach is now well established for the fabrication of advanced copper interconnects. However, as ultralarge integration progresses, process evolutions are mandatory to face the new challenges raised by feature size reduction. In this article, the extendibility of the copper deposition processes at the 32nm node is discussed. The PVD techniques used to grow the diffusion barriers and copper seed will probably have to be replaced by conformal processes. If ALD seems to be a promising solution for barrier deposition, the fabrication of an ultrathin and conformal seed layer is extremely challenging. Several solutions are examined and discussed. For feature filling, electrodeposition will probably remain the standard technique. However, the extension of existing solutions is challenging. What will be the metallization scheme at the 32nm node? This is surely an open question. Two main requirements will guide the selection of a process: the control of the copper/barrier interface, and most importantly the limitation of resistivity increase in the narrow lines.

D. Martin Knotter, Philips Semiconductors, Nijmegen, The Netherlands, & Jagdish Prasad, AMI Semiconductor, Pocatello, Idaho, USA

ABSTRACT

As new materials are introduced in semiconductor manufacturing at future technology nodes, new substrate cleaning processes are needed to meet the contamination requirements posed by ever shrinking geometries. Substrate cleaning requirements usually involve surface contamination such as micro-roughness, particles, metals and watermarks. The cleaning process usually varies with the substrate being cleaned. Therefore, it is very helpful to the manufacturing engineers to have cleaning processes for various substrates used in the semiconductor industry in one place as a reference. It is also important to understand the fundamental principles of cleaning and drying and therefore, in this paper we also present the basic principles of these processes. We have compiled the information on the cleaning processes used for various substrates in the semiconductor industry. The purpose of this article is to serve as a reference document on cleaning processes and chemistries used for various substrates in semiconductor manufacturing.

Dilip Patel, Intel assignee, ISMI, USA, & Milton Godwin, ISMI, Austin, Texas, USA

ABSTRACT

New issues have appeared recently in the landscape of defect detection and review. A need to examine defects in the bevel-edge portion of the wafer has grown in proportion to the recoverable edge ‘real estate' on larger wafers. Further, inherent limitations to in-line elemental analysis have been identified, using scanning electron microscopy/energy-dispersive X-ray spectroscopy (SEM/EDS), as defects of interest become smaller than 100nm in diameter. This article recounts how International SEMATECH Manufacturing Initiative (ISMI) has examined these issues, conducting surveys of vendors and analysis laboratories to seek pathways to enable new and more promising techniques of inspection and review.

H. Kraus, F. Kovacs & L. Archer, SEZ AG, Draubodenweg, Villach, Austria; & J. Snow, M. Claes, V. Paraschiv, R. Vos, P. W. Mertens, S. De Gendt & M. Heyns, IMEC, Leuven, Belgium

ABSTRACT

Selective removal of Hf-based high-k material from the source and drain areas is one of the challenges for the integration of these materials in the front-endof-line (FEOL) process flow. On the one hand, they are usually very difficult to etch, and on the other hand, just a small loss of oxide and silicon can be tolerated. A novel dry-enabled wet etch solution is presented that can very effectively, and with high selectivity, remove unwanted high-k dielectric. This approach leads to minimal Si recess and oxide loss. Furthermore, the application of this etch is compared for both immersion and single-wafer approaches and it shows that a single wafer solution provides a more selective alternative to immersion. Etch rates and selectivities are presented in detail and are further supported with TEM and electrical data. 

Jagdish Prasad, AMI Semiconductor, Pocatello, ID, USA

ABSTRACT

There are only minor changes in mateirals and structures at 65nm and therefore very little change in cleaning strategy for FEOL will be needed. Dedicated single-wafer tools for critical process steps may be needed to avoid crosscontamination. However, dedicated tools to all FEOL processes may be cost prohibitive and therfore it will be necessary to understand the processes that will require dedicated tools. Dilute and batch process will still be the process of choice for DRAM manufacturers but more single-wafer tools may be used by logic device manufacturers. 

C. Wyon, CEA-LETI, Crolles, France, J.P. Gonchond, J. Bienacel & P. Normandon, STMicroelectronics, Crolles, France, M. Hopstaken, R. Delsol, & L.F.Tz. Kwakman, Philips Semiconductors, Crolles, France

ABSTRACT

X-ray metrology techniques, which are hereafter defined as techniques using X-rays as the incident probe beam, are quickly moving from offline characterization laboratories to semiconductor fabrication lines. This article reviews applications of some X-ray metrology techniques to monitor FEOL and BEOL processes for the development of d65nm technology nodes. In-line control of ultrathin nitrided gate oxides is performed using XPS, while the development of high-k dielectrics can be accelerated using XRR and XRF. XRR is used for controlling the formation of NiSi thin films, as well as the individual thickness of Ta/TaN barrier layer. Monitoring of Cu interconnects texture is realized using XRD. Combined XRR and SAXS can provide valuable information about the porosity and pore-size distribution of ultra low-k layers.