Robert A. Binstead, Jeffrey M. Calvert & Robert Mikkola, Shipley Company, L.L.C., Marlborough, USA; Jonathan Reid & John Sukamto, Novellus Systems Inc., Tualatin, USA

ABSTRACT

The development of the copper damascene process by IBM has revolutionized the design and manufacture of advanced integrated circuits, allowing metal interconnects to shrink with each technology node while maintaining low-resistance wiring pathways. In combination with improvements in the interlayer dielectric materials, the use of copper interconnects has allowed chip designers to reduce the size of active transistor elements, and lower their operating voltage. This has resulted in an overall reduction in RC delay times, so producing smaller, faster devices with lower power requirements. In addition to improved device capabilities, each shrink in technology node has provided the opportunity to lower the cost of manufacture provided that acceptable yield and reliability can be maintained. The copper electroplating process is a key technology that has a significant impact on device yield, and the chemistries used to control the electrodeposition of copper interconnects have had to evolve to meet the stringent requirements of the semiconductor manufacturing processes. In this article we discuss some of the challenges for copper plating chemistries, and illustrate the improvements that have been realized in one of the contending chemistries intended for the sub-90nm node.

Drs. Wilbert G. M. van den Hoek, Chief Technical Officer and Executive Vice President of Integration and Advanced Development and CMP Business Group, Novellus Systems

ABSTRACT

Semiconductor devices have been steadily shrinking in size for over a quarter of a century. As a result, device speed is no longer determined by the transistor speed, but by the performance of the interconnect. To enable the continuation of device speed improvements, over the past five years the semiconductor industry has had to choose between two key new interconnect manufacturing technologies: copper interconnects, or low-k dielectric films. It chose to implement copper metallization first, because it was perceived to be the “easier” technology. Today, after two generations of devices with copper, we are still facing the low-k intermetal dielectric (IMD) challenge.

R. Singh, A. Venkateshan, & K. F. Poole, Holcombe Department of Electrical and Computer Engineering, Clemson University, Clemson, USA

ABSTRACT

In this article we describe the advantages of lamp-based RTP systems for thermal processing of Cu/low-k metallization at 65-nm nodes and beyond. The spectrum of incoherent light sources plays an important role in the design of RTP systems. As compared to furnace processing, mini-furnaces and resistive heater-based RTP systems, lamp-based RTP systems provide less process variation that leads to reduced cost of the design and improved performance, reliability, and yield of advanced semiconductor products.

R. Singh, A. Venkateshan, M. Fakhruddin & K. F. Poole, Center for Silicon Nanoelectronics, Clemson University and N. Balakrishnan & L. D. Fredendall, Dept. of Management, Clemson University

ABSTRACT

In this paper we have described the importance of single wafer processing (SWP) in semiconductor industry.. As compared to batch processing, reduced cycle time, reduced processing temperature, reduced process variation and reduced defect densities are some of the attractive features of SWP.