John H. Burnett, Zachary H. Levine & Eric L. Shirley, National Institute of Standards and Technology, Gaithersburg, MD, USA

ABSTRACT

Calcium fluoride and other crystalline fluoride materials are being exploited for latest generation lithography optics, making up a significant component of the optics of 193 nm lithography systems and being potentially the exclusive optical materials for 157 nm systems. Improvements in the crystalline material quality seemed to have brought the most troubling material property, stress-induced birefringence, into specification.

Roger H. French, Jerald Feldman, Fredrick C. Zumsteg, Michael K. Crawford, Andrew E. Feiring, Viacheslav A. Petrov, Frank L. Schadt III & Robert C. Wheland, DuPont Co., iTechnologies and Central Research and Development, Wilmington, DE, USA; Joseph Gordon & Edward Zhang, DuPont Photomasks Inc., Danbury, CT, USA

Substantial progress has been made in developing novel fluoropolymer materials for 157nm lithography. Materials with sufficient transparency at 157 nm to enable both thick single layer resists and high transmission pellicle membranes have been demonstrated. We have shown that tetrafluoroethylene (TFE)-containing 157 nm photoresist binder resins can be made that are sufficiently transparent to be used at film thickness greater than 200nm, have good photosensitivity, exhibit low outgassing upon exposure, are compatible with aqueous base development, and have etch rates comparable to PHOST resins. Optical absorbance on the order of 1.5/µm @ 157 nm should be possible for photoresits.

Geert Vandenberghe, Young-Chang Kim, Christie Delvaux, Kevin Lucas, Sang-Jun Choi, Monique Ercken & Kurt Ronse, IMEC, Leuven, Belgium; Bert Vleeming, ASML, Veldhoven, Holland

As ArF resists mature, lithographers are pushing the imaging limits as far as possible. As shown earlier, ArF lithography is getting ready for the 130nm technology node and currently even the 100nm node printability with ArF is being studied. Since high numerical aperture (NA) ArF scanners are not yet available in volume, strong enhancement techniques will be required to meet these challenging targets at lower NA (0.63NA). In this paper we give an overview of the status of 193nm lithography towards 100nm patterning of memory and logic front-end features, and explore the various enhancement techniques needed.

Jan-Willem Gemmink, Philips Semiconductors, Nijmegen, The Netherlands; Peter Zandbergen, Philips Semiconductors, Kapeldreef, Leuven, Belgium

ABSTRACT

As the ITRS roadmap confirms its accelerated pace of two years per technology node, the status and maturity of the lithography solutions upon introduction of the nodes is influenced. Though on paper the technological solutions on individual domains as mask, resist and tools are ready just in time, integration into full process flowcharts, however, is not thoroughly addressed. In this paper we will address the impact of this shrinking time window on the focus areas going from basic R&D of process step concepts
down to release of the intended solutions in process technology at product sampling. In the domain of SOC manufacturing this also implies modifications in process solutions that have to come after initial introduction of a technology. In addition we indicate how we see that the global programs as executed in various pre-competitive consortia by themselves not necessarily prepare for a smooth integration of technologies such as 157 nm or EUV lithography into manufacturing situations. We give some examples of such less
considered challenges that have to be addressed by device makers to assure robust and proven manufacturing boundaries for the use of these challenging lithography technologies.

Anja Rosenbusch, Sigma-C Inc, Campbell, CA, USA; Andreas Erdmann, Fraunhofer Institute of Integrated Circuits (IIS-B), Erlangen, Germany; Christoph Friedrich, Infineon Technologies AG, Munich, Germany

Optical extensions, laid out by Sematech and others, have implications for simulation, calling for new solutions. Phase-shifting masks need new models, to accurately predict the intensity imbalance and to forecast conditions under which defects print. This paper shows areas where the lithographer may expect strong assistance through simulation. The results of a study, using mask modelling for optimising edge topography of alternating phase shift mask are presented [1]. 

Urs Natzschka, Michael Schulz-Grosser & Rainier Schuhmann, Linos Photonics GmbH, Goettingen, Germany; Uwe Leinhos, Oliver Apel & Klaus Mann, Laser Laboratorium, Goettingen, Germany

ABSTRACT 

Semiconductor devices demand shorter wavelengths to keep optical lithography as the mainstay of device fabrication. In the deep UV optical components require ever more stringent control to obtain long working life and cost effectiveness. The causes of optical component degradation and failure are examined and the critical areas of measurement and quality control for DUV exposure systems are explained in detail. 

Yuan Zhang Ke & Phil Ware, Canon USA, Inc., Semiconductor Equipment Division, Irving, TX, USA
Kenichi Kotoku & Yuiichi Yamada, Canon, Inc., Semiconductor Production Equipment Group, Utsunomiya, Japan

ABSTRACT 

Commercial software for cost-of-ownership (CoO) analysis, such as TWO COOLTM, is suitable for generic fab equipment evaluation. But the evaluation of optical-lithography equipment and process strategies requires a more sophisticated approach. International SEMATECH has provided highly useful information on lithography throughput modelling through its CoO programmes. This article addresses the appropriateness of the TWO COOLTM and International SEMATECH lithography CoO models in terms of the architecture and assumptions that are essential to advanced lithography modelling.

Scott Jordan, Nanopositioning Technologies, Polytec PI, Inc., CA, USA

ABSTRACT

Many modern industrial technologies demand steadily increasing performance from embedded positioning subsystems. This necessitates more and more sophistication in the design, manufacture and control of nanopositioning devices and the metrology elements they contain. This paper describes the use of diamond-machined capacitive sensors of novel configuration to actively control the trajectories of nanopositioning mechanisms. A six-axis piezoelectric stage and digital control system has been developed in conjunction with these sensors and new flexure design concepts, yielding excellent positioning repeatability and accuracy with a wide range of possible applications. 

Emir Gurer, Tom Zhong, John Lewellen, Murthy Krishna & Eddie Lee,
Silicon Valley Group, Track Systems, San Jose, CA, USA

The demand for smaller and faster semiconductor devices to accommodate high density information transfer has dramatically accelerated the development of photolithography, the key device shrinkage enabling technology, and the shift from one generation to the next. Due to the shortened lifetime of each generation of semiconductor devices and the large amount of capital investment required to develop each generation of semiconductor equipment, there is an enormous economic incentive for the semiconductor industry to extend the current 248nm lithography technology towards 0.13µm geometries and below.

STEVEN M. PILGRIM, New York State College of Ceramics at Alfred University, Alfred, NY, USA

Piezoelectric materials are the unsung heroes of materials that are used by the IC fabrication engineer - hard working and reliable with minimum maintenance. The theory relating stress, strain and electric field is described and various extensively used piezoelectric materials reviewed and the application of these materials into precision equipment is examined in detail.

Hua-Yu Liu, Clive Wu & Xiaoyang Li, Numerical Technologies Inc., San Jose, CA, USA

Lithography has been the technological driver for shrinking circuits and creating finer and finer transistor gates. As silicon feature sizes continue to decrease below the wavelength of available exposure tools, reticle-based resolution enhancement techniques including optical proximity correction (OPC) and phase-shifting mask (PSM) are required for patterning features that are significantly smaller than wavelength. Infrastructure, such as software tools and mask making capability, has to be developed in order to use such technologies in production.

WOLF STAUD, Applied Materials, Inc., Santa Clara, CA, USA

Although new-generation lithography tools are entering production for advanced (0.18 micron and below) devices, mask qualification is in danger of falling behind this technological curve. With advances in inspection technology, users can now measure mask CD variation with greater accuracy than ever before, revealing systematic weaknesses in certain processing areas.

Graham Arthur, Rutherford Appleton Laboratory, Didcot, Oxon, UK; Brian Martin, Mitel Semiconductor, Plymouth, Devon, UK

The effect known as mask error factor (MEF) is investigated using the optical lithography simulation tool PROLITH/2 with a well tried and tuned set of simulation parameters. These investigations are extended to include the effect of pitch, linewidth, optical proximity correction, focus, lens aberrations, partial coherence, resist contrast, resist thickness and exposure. Through the use of focus-exposure matrices, process windows and manufacturing critical dimension (CD) budgets, the impact on reticle procurement specifications is also examined.

Dennis Capitanio, Pall Corporation, Port Washington, NY, USA

The trends toward narrower linewidths in the manufacture of integrated circuits has put an ever increasingburden on contamination control in every aspect of semiconductor fabrication. Point-of-use (POU) filtration of photoresists has been used to control particle contamination on the wafer surface during coating operations. The need for tighter filtration has led to the introduction of 0.05 µm as well as the traditional 0.10 µm membranes to control the contamination during the dispense of photoresists. With the introduction of tighter membranes for use in photoresist filtration, the end-user may have concerns that the photoresist may suffer some deleterious effects by undergoing filtration.

Ed Muzio*, Phil Seidel, Gil Shelden & John Canning, International SEMATECH, Inc., Austin, TX, USA, *Intel Corporation Assignee

The cost of ownership (CoO) has become a key parameter in the comparison of lithography technologies. This article presents some results from the CoO modelling technique used by International SEMATECH, with specific focus on cost drivers and sensitivities. The principal drivers of the CoO values are mask usage, mask cost, tool throughput, and tool cost. By examining trends in these and other areas, one can identify the areas of highest leverage for proactive cost reduction efforts.

Joe Bartolomeo & J. D. Detrempe, Rockwell Automation, Milwaukee, WI, USA

ABSTRACT

Implementing Semiconductor Equipment and Materials International (SEMI) standards for semiconductor capital equipment has traditionally been a timeconsuming and tedious process, based on proprietary software programs, and requiring custom software development. Now, off-the-shelf software products based on open systems technologies like Microsoft ActiveX controls and Visual Basic for Applications, allow developers and OEMs to create SEMI-compliant systems in weeks, rather than months, with no custom coding. Developers and OEMs can quickly deploy systems by setting up only the basic GEM requirements, like event notification and alarm messages, and can add additional capabilities when needed.

Larry Dulmage, Eddie Lee & Jae Park, Silicon Valley Group, Inc., San Jose, CA, USA.

ABSTRACT

The transition to 300 mm is fast approaching while at the same time 200 mm devices are rapidly shrinking. Additionally, the lithography roadmap with the addition of 157 nm and extreme ultra-violet (EUV) is poised to carry us to at least 50 nm. The industry must, therefore, quickly address advanced deep ultra-violet (DUV) coat/develop systems and the challenges that they present. All coat/develop systems face four fundamental problems: 1. System-induced timing delays, which impact CD performance, 2. Develop process times and contamination levels that are being extended to meet more critical geometries, 3. Thinner, more uniform resists for both single and dual-layer DUV processes, and 4. Throughput. In order to address the last three issues, we must first find a fundamental design solution for a system architecture that resolves system-induced delays, which are caused by the complex nature of today's linear tracks. 

Ralph R. Dammel, Clariant Corporation, Somerville, NJ, USA

ABSTRACT

The history of lithography in the last two decades has been dominated by the extension of the life of optical technologies. The scope of this extension has exceeded the predictions of almost any expert bold enough to forecast the development of exposure techniques in the early 1980s, when questions about the future of optical lithography were first raised.

Ingrid B. Peterson, KLA-Tencor Corporation, Milpitas, CA, USA

One of the challenges facing the implementation of DUV and advanced i-line lithography processes in production is that of maintaining low defect density in order to minimize the impact on yield. Yield depends on the complex interaction between design, CD and overlay control, films, electrical parameters, and defects. As the geometries shrink and the chip size increases, defect reduction becomes increasingly important.

Kurt Ronse & Luc Van Den Hove, IMEC, Leuven, Belgium

Resolution enhancement techniques for optical lithography have been investigated for many years. Pioneering work on phase shifting masks for optical lithography was reported in 1982 by M.D. Levenson, ref. [1], but the real boom of research on resolution enhancement techniques took place in the early 90s. Nevertheless, more than 8 years later, only very few of these techniques are being used in the production of integrated circuits. In this paper, the status of the various enhancement techniques is reviewed, their capabilities illustrated and their challenges discussed. In conclusion, an attempt is made to predict the insertion of these techniques in manufacturing.