Vivek M. Prabhu & Eric K. Lin, National Institute of Standards and Technology, Gaithersburg, USA

ABSTRACT

Advances in optical lithography, using chemically amplified photoresists, have continued to meet ITRS [1] goals. However, lineedge roughness (LER) and critical dimension (CD) control remain technical challenges for upcoming 65nm and 45nm nodes because both the image resolution and the thickness of the imaging layer now approach the macromolecular dimensions characteristic of the polymers used in the photoresist film. With accompanying decreases in film thickness, the photoresist/ substrate and photoresist/air interfacial properties, and component distribution increasingly affect the overall performance of a photoresist. New measurement methods are needed to address fundamental issues that may limit the development of future photoresists. 

Mark E. Mason, Texas Instruments Incorporated, Dallas, Texas, USA

ABSTRACT

In 1965, Gordon Moore set a path for lithographers that has led directly to the abundant use of resolution enhancement technologies (RETs) for patterning semiconductor devices. Not surprisingly, these RETs have a real cost in terms of computation times, complexity, license fees, and support manpower. The International Sematech Cost of Ownership (CoO) analysis [1] can be extended to estimate the impact of RETs on overall lithography CoO and on the cost per modern semiconductor wafer, which appears to be around $10/RET level for a high-volume ASIC case. 

M. Dilger, F. Gans, & J. H. Peters, Advanced Mask Technology Center GmbH & Co. KG

ABSTRACT

Metrology is not only used to measure the size of structures on photolithography masks for a verification of conformance with the customer specifications. A major part of the metrology tool time is usually devoted to process development and pattern structures deviating from the ideal shapes need to be analysed for process tuning. Current tools usually treat the mask as a 2-dimensional object, which for the future technologies is no longer a valid concept. Furthermore, in some cases there is a strong interference between the object to be measured and the measurement technique itself. AMTC is working on concepts and measuring methods to accelerate the process development. 

Ron A. Synowicki, Greg K. Pribil, Gerry Cooney, Craig M. Herzinger & Steven E. Green, J. A. Woollam Co., Inc.

ABSTRACT

As immersion lithography continues to develop at a rapid pace it will be necessary to determine the refractive index n and k of immersion fluids since the fluid becomes an important element of the optical system. The refractive index of several candidate immersion fluids for 193nm and 157nm immersion lithography is demonstrated using the prismminimum deviation technique. Measurements have been implemented on a commercially available variable-angle spectroscopicellipsometer system capable of operation into the vacuum ultraviolet. Results compare very well to high-accuracy reference measurements performed at NIST. 

Mark Osborne, Editor-in-chief, Semiconductor Fabtech

ABSTRACT

The 29th SPIE Annual International Symposium on Microlithography, held in Santa Clara California in late February 2004, is always of significance due to the crucial role lithography and its associated steps and enhancements play in realising Moore's Law. The gathering this year was of particular significance due to the anticipated insight that leading lithographers from around the world would shed on the very latest developments with ArF immersion lithography. Going from concept to modelling and alpha-tool phase in less than two years has been a remarkable feat. 

Ming Yeon Hung, Taiwan Semiconductor Manufacturing Company and Xuemei Chen, Kelly Kuo, Steven Fu, Viral Hazari, Kevin Monahan, Mike Slessor & Amir Lev, KLA-Tencor Corp, and George Shanthikumar, Zhoujie Mao & Shiming Deng, University of California (Berkeley)

ABSTRACT

With shrinking design rules and the transition to 300-mm wafers, the risk and cost associated with process excursions become more severe. With the increased number and value of transistors per wafer, any process or product excursion that goes undetected or is not forestalled, implies significant material at risk and unnecessary production cost. Therefore, a systematic approach to excursion management that ensures effective detection, identification, and reduction of process excursions is essential for realizing the productivity and cost benefits of the technology shifts. In this article, we describe excursion management as applied to overlay in lithography, in the context of a total lithography metrology ROI analysis framework for 300-mm high-volume production.

Janardhan Devrajan & Neil Fernandes, Novellus Systems

ABSTRACT

The key driver for photoresist strip applications in semiconductor fabs has always been lowest cost of ownership with maximum reliability. The unique multi-station sequential processing architecture of the GAMMA platform has enabled the industry's highest capital productivity, while providing the process engineer with the flexibility to include a number of varied applications such as bulk photoresist strip, high dose implant strip, photoresist etchback, and soft silicon etch on the same platform. This article discusses the technical challenges of these processes and describes the product features that enable simple approaches to meeting them without compromising on the system throughput. 

Mark Slezak, JSR Micro, Inc.

ABSTRACT

As critical dimensions continue to shrink, the technical challenges for 193-nm lithography continue to increase. In order for ArF lithography to support the 65-nm node and below, resist suppliers and lithographers will need to identify ways to improve resolution down to half-pitches of 70 nm as well as 70-80 nm isolated trenches and contact hole patterns. Potential line collapse, increased line edge roughness (LER), post-exposure bake (PEB) sensitivity and the need for improved etch resistance are some of the most common issues lithographers face when moving toward the line widths required for the 45-nm node. 

Phillip Walsh, George Li, & A. Forouhi, n&k Technology, Inc.

ABSTRACT

We present a method based on broadband spectrophotometry in conjunction with Forouhi-Bloomer dispersion equations and hybridrigorous coupled wave analysis (RCWA) for monitoring film thickness, film optical properties, trench parameters, and phase shift in phase-shift masks. The method, known as the n&k method, has certain advantages over conventional metrology in terms of throughput and suitability for integration into the mask creation process. At the same time, the n&k method has demonstrated excellent correlation with conventional metrology methods. 

Dr. Peter Kuschnerus, E-Beam Mask Repair Systems, LEO Electron Microscopy Group

ABSTRACT

The quality of photo masks used in chip fabrication is a key factor determining the quality and yield achieved in wafer fabs. In order to achieve reduced feature sizes and to enhance integration depth, shorter wavelengths, i.e. 193nm and 157nm are used. Furthermore, advanced and complex enhancement techniques like optical proximity correction (OPC) features or phase-shift masks (PSM) are necessary. This results in challenging needs for advanced mask repair, in new materials, higher accuracies and precision and higher demands to VUV transmission.  

Mark Osborne, Editor-in-Chief, Semiconductor Fabtech 

ABSTRACT

Lithography technology issues tend to dominate the processing landscape due to their Moore’s Law fulfilment capability. The  Roadmap looked like it was slipping dangerously as 157nm development programs became embroiled in severe technical hurdles, and chip manufacturers were reluctant to commit to multi-million dollar preliminary orders for the next generation of DUV tools. Extending 193nm lithography is rapidly becoming the de facto technology of choice, both for the tool vendor and the chip fabricator. However, a race is on to prove that 193nm Immersion lithography is a viable route that could see 157nm bypassed altogether and allow a straight path
to EUV. At SEMICON West (July 2003), the immersion lithography debate dominated the proceedings with tool vendors jockeying for
position. Here, we review the current state of play, the key challenges and the possible outcome by year-end.

Vivek Bakshi, Jerry Collins, N. V. Edwards, Kevin Kemp, Pat Marmillion, Jan-Peter Urbach, Thomas White & Obert Wood, International SEMATECH

ABSTRACT

The purpose of this article is to provide an update of the current status and most recent advances in each of the specific areas of sources, masks, optics, photoresists and microexposure tool for extreme ultraviolet lithography. The article is therefore organized according to these topics, with a brief discussion of the issues surrounding each, the current development status, and future outlook. A sustained study on the development of industry infrastructure for EUVL is underway at International SEMATECH. Although significant challenges remain, progress is being made on various technical fronts. 

Yuichi Yamada, Canon, Inc. & Toshihiro Oga, Canon U.S.A., Inc.

ABSTRACT

Lithography, the primary enabling technology of the semiconductor industry, is rapidly moving from 130nm to 90nm for volume
production, and 65nm for R&D. Suppliers of lithography systems are being challenged to deliver superior imaging performance at ever-higher productivity at two-year design shrink intervals. To ensure a balance of performance and cost, the manufacturers of leading-edge devices are pursuing a mix-and-match strategy using new very high NA (0.85) 193nm (ArF) scanners for critical layers, 248nm (KrF) for semicritical layers and i-line for non-critical. This paper outlines Canon’s exposure tool strategy for the 90nm to 65nm
era, with emphasis on platform design fundamentals, imaging/machine performance, and cost of ownership.

Ralph R. Dammel, Clariant Corporation, New Jersey, USA

ABSTRACT

The improvements in photoresists required to meet the ITRS roadmap’s goals are discussed for the 100nm node and beyond. The main issues as resist technologies are being introduced at half-wavelength resolution are found to be low DOF, mask error  enhancement factors (MEEF), line edge roughness (LER), line collapse at high aspect ratios, particle and defectivity issues, PEB sensitivity requirements, as well as general polymer physics and chemistry limitations, such as issues related to absorbance and dry etch stability. It is found that while some solutions are on the horizon for the nearer nodes of the roadmap, there are currently no concepts to deal with some of the extremely demanding roadmap goals for the out-years.

J. N. Hilfiker, J.A.Woollam Co., Inc. Lincoln, NE, USA; F. G. Celii, W. D. Kim, E. A. Joseph, C. Gross, T. Y. Tsui, R. B.Willecke & J. L. Large, Texas Instruments, Dallas, TX, USA; D. A. Miller, International SEMATECH, Austin, TX, USA

ABSTRACT

New SE tools measuring into the vacuum ultraviolet (VUV) allow accurate thin film metrology at193 and 157nm. This article reviews characterization of photoresist, anti-reflection, and hardmask candidate coatings using SE. Optical characterization of these layers allows simulation and optimization of the lithography process. 

S. Satyanarayana & R. Berger, International SEMATECH, Austin TX; K. Brennan, Texas Instruments Assignee to SEMATECH; T. Jacobs, Philips Assignee to SEMATECH

ABSTRACT

This article presents general guidelines for preventing resist poisoning during patterning of low k dielectrics.[1] The patterning approaches discussed here are 248nm and 193nm lithography. The low k materials considered here include both CVD and spin-on types, which are the two major categories of low k materials being considered by IC manufacturers. Early work was based on the assumption that poisoning was caused by interaction of the resist with the out-gassing products of the low k films [2]. Here it is shown that a more comprehensive study of the interactions of the resist with the process chemicals and the materials in the film stack is required to fully understand the poisoning problem. 

Veerle Van Driessche & Grozdan Grozev, Assignees of ARCH Chemicals N.V. to IMEC’s 193nm Lithography Programme; Kevin Lucas, Motorola, Austin, TX, USA; Frieda Van Roey, IMEC, Leuven, Belgium; Plamen Tzviatkov, ARCH Chemicals N.V., Zwijndrecht, Belgium

ABSTRACT 

Manufacturable process windows for the small contact dimensions of the 100 nm lithography generation are well beyond the capability of current 193 nm resist and exposure tool processes. Even with next generation very high NA (>0.7) 193 nm
exposure tools, simulations indicate that these contact sizes are not obtainable with standard processing techniques. Therefore, we have investigated the feasibility of using a 193 nm resist reflow technique to obtain small contact hole sizes. We have chosen the Thin Imaging System 2000 (TIS2000) of ARCH Chemicals for investigation. This resist provides good process latitudes and excellent etch selectivity and has a much lower glass temperature (Tg) compared to single layer 193 nm resists. This work will show the flow characteristics and the reproducibility of the flow process. Furthermore, the impact-of-resist flow on Focus-
Exposure windows, proximity and proximity-uniformity, CD-uniformity over the wafer and mask error factor will be shown using a binary mask. These results will be compared with those obtained with a 6% attenuated phase shift mask. Additional experimental results will highlight profiles after oxide etch.

Erik N. Hoggan, Brian J. Novick & Ruben G. Carbonell, North Carolina State University, Raleigh, NC, USA; Joseph M. Desimone, University of North Carolina at Chapel Hill, Chapel Hill, NC, USA

ABSTRACT

The majority of coatings for processes in integrated circuit manufacturing are formed using water, organic solvents or dry deposition techniques such as chemical vapour deposition (CVD). We are investigating the formation of high quality coatings using a high-pressure condensed gas, carbon dioxide CO₂). Coating techniques using condensed CO₂ may help eliminate many of the environmental and other challenges inherent in conventional solvent systems by taking advantage of the unique properties of this
high-pressure fluid.

Corinne Miramond, Dominique Goubier & Michael Chomat, STMicroelectronics, Crolles, France; Yorick Trouiller, LETI-CEA, France; Yves Rody, Philips Semiconductors, France; Olivier Toublan, Mentor Graphics

ABSTRACT

The introduction of strong optical proximity correction (OPC) to process 0.13 μm designs and below has induced a new data-processing flow. This has been implemented at STMicroelectronics Crolles using a Mentor Graphics software suite. To deal more easily with model-based corrections and additional verification on critical layers, a separation of the design database into critical and non-critical layers has been introduced. The resist model and the correction parameters needed during the OPC processing are developed in an iterative way. File sizes and data-processing time are the main issues in mask data preparation. The impact on mask manufacturing is also addressed in this article.

Kay Lederer, Steffen Hornig & Ralf Schuster, Infineon Technologies SC300, Dresden, Germany 

ABSTRACT 

In this paper, we discuss implications currently relevant to 300mm lithography resist processing. The larger wafer size has highlighted a range of resist process issues that were not encountered at the smaller wafer sizes. In particular, resist thickness fluctuations around the edge area of a silicon wafer typically occur if high spin speeds are applied during the coating process. 300mm coating processes are particularly prone to the occurrence of such spin marks as the operating range of applicable spin speeds is lower in comparison to processes applied to smaller sized wafers. We show in our example how such local resist thickness fluctuations impact the product yield. The paper will also show how we investigated a novel resist development process based on a new developer dispense nozzle to combat this problem.