R. Singh, T. Boland, R. Mulye, G. Gaur, J.Steelman, D. Arya, N. Srinidhi and P.Deshmukh, Holcombe Department of Electrical and Computer Engineering and Center for Silicon Nanoelectronics, Clemson University, South Carolina, USA

ABSTRACT

Directed self-assembly (DSL) has been projected as a potential solution to the critical dimension limit faced by conventional lithography techniques. In this paper we review the literature data on directed self-assembly to investigate the challenges in application of self-assembly techniques for mainstream semiconductor manufacturing.  Based on fundamental considerations and process-induced defects of DSL, it is highly unlikely that DSL will ever enter mainstream semiconductor manufacturing.

Iris Mäge & Uwe Seifert, Qimonda AG, Dresden; Barry Saville & Martin Tuckermann, KLA-Tencor GmbH, Dresden

ABSTRACT

With the introduction of sub-100nm design rules, and especially 193nm photolithography, the development of new monitoring strategies is becoming increasingly important and necessary as new materials, new tools and new process challenges are introduced. Micro after-develop inspection (µADI) is a big step forward for photolithography defect monitoring as well as for integrated process learning.

Michael D. Archuletta, Chris Constantine & Dave Johnson, Unaxis Semiconductors, Florida, USA

ABSTRACT

Wafer dimensions continue to accelerate downward towards ever smaller features and the legendary Moore’s Law is still valid for current silicon devices. As wafer IC dimensions approach the physical limitations of silicon physics, the lithography techniques used to print these patterns on silicon become very difficult to perform. This article describes advances in this area down to 65-nm sizes.

Uzodinma Okoroanyanwu, AMD, USA; Remo Kirsch & Marcel Grundkowski, AMD Fab 36, Germany; Rene Wirtz & Wolfram Grundke, AMD Saxony LLC, Germany

ABSTRACT

The product pilot lines of the leading-edge IC fabs in the world today are fine tuning their immersion lithography processes for patterning devices at the 45nm technology node, in  preparation for high volume production in 2008. Within a relatively short time,  immersion lithography has made the transition from a mere research curiosity just three years ago to a technology that has shown significant and demonstrable device yield, and is now poised for large scale deployment across the 45nm node device product line. This is a remarkable achievement, which underscores the enormous progress made in the realm of defectivity and overlay control – the twin achilles heels of immersion lithography.

By Mark Thirsk and Mike Corbett, Linx Consulting LLC, USA

ABSTRACT

For at least the last 20 years, lithography has enabled the increase in density that has sustained the rapid increase of functionality that has been key in the development of the electronics industry.  Today, lithography faces physical, chemical and business challenges in delivering the patterning densities required by the ITRS (International Technology Roadmap for Semiconductors). The pressure to achieve the next node (even in name) before the competition accelerates the development progress from an anticipated 3-year to a 1.5- or 2-year cycle is intense.  This pace to improve resolution puts huge strains on the lithographer, and indeed on all involved in transferring the pattern to the substrate.  However, the need to meet future requirements is leading to several new trends in lithography and patterning.

By Monique Ercken, Roel Gronheid, Ivan Pollentier and Philippe Leray, IMEC, Belgium

ABSTRACT

193nm immersion lithography is rapidly moving towards industrial application. A large number of tools has been installed worldwide and they, of course, will require immersion-capable processing to be available. Resist processes without protective topcoats are the favored solution for introduction into mass production, from a cost-of-ownership perspective. This approach adds at least two extra constraints to the list of resist requirements: low leaching and high dynamic contact angle. Various components in the resist show (before and/or after exposure) at least some solubility in water and therefore are likely to leach into the water. This can be a source for lens contamination and resist defectivity. Next to that, the dynamic ‘receding’ contact angle is considered as one of the key parameters to control the amount of water droplets left behind on the wafer surface after exposure. These factors make the selection of a resist for processing without a topcoat as a barrier layer quite challenging, because now minimized leaching, acceptable contact angle and superior overall litho performance (at half-pitches as small as 45nm) are to be met simultaneously. In this paper, we will address whether current state-of-the-art dedicated immersion resists without topcoat are ready for use in production. An overview will be given on the performance of these materials and for some selected parameters a comparison will be made with a process including a topcoat.

By Eitan Herzel and Mike Adel, KLA-Tencor Corporation, Israel

ABSTRACT

Overlay control has always played an important role in semiconductor fabrication, helping to monitor layer-to-layer alignment on multi-layer device structures. Misalignment of any kind implies short circuits and connection failures, which in turn impact fab yield and profit margins. The importance (and associated difficulty) of controlling overlay has grown exponentially since 90nm, but robustness of overlay measurements has become especially critical as logic and memory IC manufacturers now ramp into high-volume 45nm production, where overlay budgets are shrinking fast (see Figure 1) from a relatively relaxed 30% of design rules down to 10% or even less.

By Terrence E. Zavecz, TEA Systems, Philadelphia, USA

ABSTRACT

The International Technology Roadmap for Semiconductors' history details the growing complexity of device design and the latest device-manufacturer's techniques for tuning their process for each new design generation.  In spite of the current desire to incorporate techniques termed 'Design for Manufacture' into manufacturing, simulations and the design cycle, they do little more than optimize feature quality for ideal exposure conditions while testing for shorts, opens and overlay problems over process variations.

Stefan Hempel, Steffen Volt & Wolfram Grundke, AMD, Dresden, Germany

ABSTRACT

Lithography scanners represent the most cost-intensive tools in a semiconductor facility. Productivity improvements on litho clusters not only increase the whole lithography productivity but also enhance the entire fab performance. To ensure a cost-efficient lithography process, the scanner should always represent the internal bottleneck within a linked lithography cell. Therefore, it is specifically important to maximize the scanner performance and its output. This paper provides an overview of methods and approaches to increase the productivity of linked lithography cells. 

Peter Rabkin, Michael Hart & Daniel Gitlin, Xilinx, Inc.

ABSTRACT

Leading fabless companies produce designs for cutting edge technologies almost on a par with leading integrated device manufacturers (IDMs). Foundries have evolved from making devices one to three nodes behind IDMs to funding leading-edge R&D and manufacturing chips using the most advanced processes. The key fabless/foundry challenge - how to produce manufacturable designs for cutting edge technology nodes to meet time-to-yield and time-to-volume requirements - is being overcome by an extensive effort broadly called Design For Manufacturability (DFM). Different from IDM requirements, fabless DFM requires addressing a number of additional issues, such as obtaining and utilizing proprietary manufacturing information in the course of the design. That, in turn, requires deep understanding of process-to-design interactions, new process characterization and modeling methodologies, EDA tools, data structures, process models, encryption techniques, etc. Solving these issues and enabling sufficient information flow between design and manufacturing is critical for the overall competitiveness of the fabless/foundry business model. 

Monique Ercken, Mireille Maenhoudt & Mieke Van Bavel*, IMEC, Leuven, Belgium  (*scientific editor)

ABSTRACT

Lithography experts, IC manufacturers, tool and material suppliers are moving full speed ahead to bring immersion lithography into production for the 45nm technology node.  However, both resist leaching and immersion related defectivity remain a source of concern.  For the latter, a fundamental understanding of the sources and mechanisms involving defect formation is highly demanded.  Recently, great progress has been achieved in the understanding and mitigation of both scanner- and material-related immersion defectivities.  In addition, resist leaching has been characterized in more detail and the pros and cons of using a top coat to mitigate leaching have been evaluated.  The challenges in these areas that remain to be solved before bringing immersion into mass production have been identified.

Axel Zibold, Ulrich Stroeßner, & Andrew Ridley, Carl Zeiss SMS GmbH, Germany, & Vicky Philipsen, Joost Bekaert, & Live van Look, IMEC, Belgium

ABSTRACT

Immersion lithography offers the semiconductor industry an opportunity to extend the current ArF processes to smaller half-pitch nodes before switching to a shorter exposure wavelength. The transition to immersion will require increased attention to the photomask along with new effects influencing the aerial image formation as the numerical apertures (NA) of scanners move up to at least 0.93 and beyond. Feature sizes on the photomask become comparable to, or even smaller than, the wavelength and begin to act like wire grid and/or other types of polarizers, which can lead to potentially serious polarization effects. 

Skip Miller, Hans Kattouw & Frank van Bilsen, ASML, Netherlands, & Axel Nackaerts & Staf Verhaegen, IMEC, Belgium

ABSTRACT

Productivity improvements of output in terms of square centimeters per unit time have increased more than 50-fold over the past 20 years. In addition to delivering a lower cost of ownership, the increased productivity also improves fab efficiency. Imaging and overlay improvements deliver IC industry value by enabling aggressive design rules and maximizing die yield. In this paper, a typical industry SRAM structure is used to look at the sensitivity analysis regarding die area compared to overlay and imaging performance. It is found that imaging or resolution improvements via NA and k1 have a big impact on the die area and resulting possible die per wafer. In the example studied, there was a 3.4% gain in die per wafer for every 1% reduction in k1. Overlay reduction has a significant impact on die area as well. In this analysis we concluded that there is approximately a 0.2% gain in die area, or die per wafer, for every 1% reduction in overlay. Finally, die yield sensitivity vs. improvements in imaging and overlay is investigated. At the imaging or overlay specification, the slope of the yield curve is very steep. For the 45nm node, there was an approximately 5% improvement in yield for every 1% reduction in CDU and overlay. 

John A. Allgair, Freescale assignee to International SEMATECH Manufacturing Initiative (ISMI), Austin, TX, USA, Benjamin D. Bunday, Mike Bishop & Pete Lipscomb, International SEMATECH Manufacturing Initiative (ISMI), Austin, TX, USA

ABSTRACT
There are numerous metrology challenges facing photolithography for the 45nm technology node and beyond in the areas of critical dimension (CD), overlay and defect metrology. Many of these challenges are identified in the 2005 International Technology Roadmap for Semiconductors (ITRS) [1]. The Lithography and Metrology sections of the ITRS call for measurement of 45/32/22/18nm generation linewidth and overlay. Each subsequent technology generation requires less variation in CD linewidth and overlay control, which results in a continuing need for improved metrology precision. In addition, there is an increasing need to understand individual edge variation and edge placement errors relative to the intended design. This is accelerating the need for new methods of CD and overlay measurement, as well as new target structures. This article will provide a comprehensive overview of the CD and overlay metrology challenges for photolithography, taking into account the areas addressed in the 2005 ITRS for the 45nm technology generation and beyond. 

Kevin Monahan & Brian Trafas, KLA-Tencor Corporation, Milpitas, California, USA

ABSTRACT

Immersion lithography at 193 nm has emerged as the leading contender for critical patterning through the 32-nm technology node. Super-high NA, along with attendant polarization effects, will require reoptimization of virtually every resolution enhancement technology and the implementation of advanced process control at intrawafer and intrafield levels. Furthermore, interactions of critical dimensions, profiles, roughness, and overlay between layers will impact design margins and become severe yield limiters. 

Jan Makos-Brotherton, Texas Instruments Assignee to SEMATECH, Will Conley, Freescale Semiconductor Assignee to SEMATECH, Kim Dean, SEMATECH, Jeff Meute IBM Assignee to SEMATECH, & Karen Turnquest, AMD Assignee to SEMATECH, Austin, TX, USA

ABSTRACT

As the semiconductor industry struggles to maintain the pace set by Moore's Law, the lithography research community must take on new challenges to ensure robust resist performance. Current research continues on parallel paths for extreme ultraviolet (EUV) and 193-nm immersion technologies, stretching available resources to solve critical issues in line-edge roughness (LER), sensitivity, resolution, etch resistance, and optics contamination. SEMATECH is making progress in solving key issues of cutting-edge technologies with the help and cooperation of suppliers, universities, national labs, and other consortia. 

Roel Gronheid, IMEC, Lithography Department, Kapeldreef, Leuven, Belgium, & Rida Al-Horr, Dionex Corporation, Sunnyvale, CA, USA

ABSTRACT

This article describes a new technique for in-line purge gas monitoring for acid contaminants. The technique is applied to the inlet and outlet channels of the active charcoal filters on an ASML PAS5500/1100 193- nm scanner. For this study the focus was on NOx and SOx contaminants. They were observed to fluctuate over time and to be present at high levels (0.5-3 ppb) at the filter inlet. At the outlet, the residual contamination could be measured and the average was found to be ~35 ppt for NO/HONO and ~2 ppt for SOx, corresponding to filtering efficiencies of 98% and 99.8%, respectively. 

Robin Danfelt, Senior Contamination Control Engineer, Nikon Precision, Belmont, CA, USA

ABSTRACT

It is clear that 193nm lithography photoresists and scanner optical components, as well as masks, are far more sensitive to airborne molecular contaminants (AMC) than those used in earlier lithography generations. However, even older equipment can be significantly affected by AMC. Additionally, although a fab may have AMC levels under control, excursions in the ambient environment or tool pressure differentials may impact process and equipment and, over time, may result in a significant effect on lithographic illumination power or uniformity. 

Vladimir A. Ukraintsev, Silicon Technology Development, Texas Instruments Inc., Dallas, TX, USA

ABSTRACT

The International Technology Roadmap for Semiconductors (ITRS) predicts that atomic force microscopy (AFM) will become an in-line metrology tool starting at the 65nm technology node. Others argue that AFM is not suitable beyond the 65nm node due to probe-size limitations [1]. This article examines the current state of AFM in semiconductor technology development and manufacturing. Some key applications of AFM are reviewed. This current state is contrasted with upcoming requirements and limitations of metrology tools. The unique role of AFM in establishing across-CD metrology correlation and accuracy is emphasized.

S.V. Sreenivasan, Ian McMackin, Frank Xu, David Wang & Nick Stacey, Molecular Imprints, Inc., Austin, Texas, USA and Doug Resnick, Motorola Research Laboratories, Tempe, AZ, USA

ABSTRACT

This article is concerned with a novel step-and-repeat nano-replication technique based on low-viscosity UV-curable liquids. This leads to significantly lower process defects. Further, the low viscosity liquids allow for nanoscale in-situ alignment corrections in the liquid just prior to UV curing, leading to improvements in alignment capability.