Emir Gurer, Tom Zhong, John Lewellen, Murthy Krishna & Eddie Lee,
Silicon Valley Group, Track Systems, San Jose, CA, USA

The demand for smaller and faster semiconductor devices to accommodate high density information transfer has dramatically accelerated the development of photolithography, the key device shrinkage enabling technology, and the shift from one generation to the next. Due to the shortened lifetime of each generation of semiconductor devices and the large amount of capital investment required to develop each generation of semiconductor equipment, there is an enormous economic incentive for the semiconductor industry to extend the current 248nm lithography technology towards 0.13µm geometries and below.

STEVEN M. PILGRIM, New York State College of Ceramics at Alfred University, Alfred, NY, USA

Piezoelectric materials are the unsung heroes of materials that are used by the IC fabrication engineer - hard working and reliable with minimum maintenance. The theory relating stress, strain and electric field is described and various extensively used piezoelectric materials reviewed and the application of these materials into precision equipment is examined in detail.

Hua-Yu Liu, Clive Wu & Xiaoyang Li, Numerical Technologies Inc., San Jose, CA, USA

Lithography has been the technological driver for shrinking circuits and creating finer and finer transistor gates. As silicon feature sizes continue to decrease below the wavelength of available exposure tools, reticle-based resolution enhancement techniques including optical proximity correction (OPC) and phase-shifting mask (PSM) are required for patterning features that are significantly smaller than wavelength. Infrastructure, such as software tools and mask making capability, has to be developed in order to use such technologies in production.

WOLF STAUD, Applied Materials, Inc., Santa Clara, CA, USA

Although new-generation lithography tools are entering production for advanced (0.18 micron and below) devices, mask qualification is in danger of falling behind this technological curve. With advances in inspection technology, users can now measure mask CD variation with greater accuracy than ever before, revealing systematic weaknesses in certain processing areas.

Graham Arthur, Rutherford Appleton Laboratory, Didcot, Oxon, UK; Brian Martin, Mitel Semiconductor, Plymouth, Devon, UK

The effect known as mask error factor (MEF) is investigated using the optical lithography simulation tool PROLITH/2 with a well tried and tuned set of simulation parameters. These investigations are extended to include the effect of pitch, linewidth, optical proximity correction, focus, lens aberrations, partial coherence, resist contrast, resist thickness and exposure. Through the use of focus-exposure matrices, process windows and manufacturing critical dimension (CD) budgets, the impact on reticle procurement specifications is also examined.

Dennis Capitanio, Pall Corporation, Port Washington, NY, USA

The trends toward narrower linewidths in the manufacture of integrated circuits has put an ever increasingburden on contamination control in every aspect of semiconductor fabrication. Point-of-use (POU) filtration of photoresists has been used to control particle contamination on the wafer surface during coating operations. The need for tighter filtration has led to the introduction of 0.05 µm as well as the traditional 0.10 µm membranes to control the contamination during the dispense of photoresists. With the introduction of tighter membranes for use in photoresist filtration, the end-user may have concerns that the photoresist may suffer some deleterious effects by undergoing filtration.

Ed Muzio*, Phil Seidel, Gil Shelden & John Canning, International SEMATECH, Inc., Austin, TX, USA, *Intel Corporation Assignee

The cost of ownership (CoO) has become a key parameter in the comparison of lithography technologies. This article presents some results from the CoO modelling technique used by International SEMATECH, with specific focus on cost drivers and sensitivities. The principal drivers of the CoO values are mask usage, mask cost, tool throughput, and tool cost. By examining trends in these and other areas, one can identify the areas of highest leverage for proactive cost reduction efforts.

Joe Bartolomeo & J. D. Detrempe, Rockwell Automation, Milwaukee, WI, USA

ABSTRACT

Implementing Semiconductor Equipment and Materials International (SEMI) standards for semiconductor capital equipment has traditionally been a timeconsuming and tedious process, based on proprietary software programs, and requiring custom software development. Now, off-the-shelf software products based on open systems technologies like Microsoft ActiveX controls and Visual Basic for Applications, allow developers and OEMs to create SEMI-compliant systems in weeks, rather than months, with no custom coding. Developers and OEMs can quickly deploy systems by setting up only the basic GEM requirements, like event notification and alarm messages, and can add additional capabilities when needed.

Larry Dulmage, Eddie Lee & Jae Park, Silicon Valley Group, Inc., San Jose, CA, USA.

ABSTRACT

The transition to 300 mm is fast approaching while at the same time 200 mm devices are rapidly shrinking. Additionally, the lithography roadmap with the addition of 157 nm and extreme ultra-violet (EUV) is poised to carry us to at least 50 nm. The industry must, therefore, quickly address advanced deep ultra-violet (DUV) coat/develop systems and the challenges that they present. All coat/develop systems face four fundamental problems: 1. System-induced timing delays, which impact CD performance, 2. Develop process times and contamination levels that are being extended to meet more critical geometries, 3. Thinner, more uniform resists for both single and dual-layer DUV processes, and 4. Throughput. In order to address the last three issues, we must first find a fundamental design solution for a system architecture that resolves system-induced delays, which are caused by the complex nature of today's linear tracks. 

Ralph R. Dammel, Clariant Corporation, Somerville, NJ, USA

ABSTRACT

The history of lithography in the last two decades has been dominated by the extension of the life of optical technologies. The scope of this extension has exceeded the predictions of almost any expert bold enough to forecast the development of exposure techniques in the early 1980s, when questions about the future of optical lithography were first raised.