Mark Osborne, Editor-in-chief, Semiconductor Fabtech

ABSTRACT

The 29th SPIE Annual International Symposium on Microlithography, held in Santa Clara California in late February 2004, is always of significance due to the crucial role lithography and its associated steps and enhancements play in realising Moore's Law. The gathering this year was of particular significance due to the anticipated insight that leading lithographers from around the world would shed on the very latest developments with ArF immersion lithography. Going from concept to modelling and alpha-tool phase in less than two years has been a remarkable feat. 

Ming Yeon Hung, Taiwan Semiconductor Manufacturing Company and Xuemei Chen, Kelly Kuo, Steven Fu, Viral Hazari, Kevin Monahan, Mike Slessor & Amir Lev, KLA-Tencor Corp, and George Shanthikumar, Zhoujie Mao & Shiming Deng, University of California (Berkeley)

ABSTRACT

With shrinking design rules and the transition to 300-mm wafers, the risk and cost associated with process excursions become more severe. With the increased number and value of transistors per wafer, any process or product excursion that goes undetected or is not forestalled, implies significant material at risk and unnecessary production cost. Therefore, a systematic approach to excursion management that ensures effective detection, identification, and reduction of process excursions is essential for realizing the productivity and cost benefits of the technology shifts. In this article, we describe excursion management as applied to overlay in lithography, in the context of a total lithography metrology ROI analysis framework for 300-mm high-volume production.

Janardhan Devrajan & Neil Fernandes, Novellus Systems

ABSTRACT

The key driver for photoresist strip applications in semiconductor fabs has always been lowest cost of ownership with maximum reliability. The unique multi-station sequential processing architecture of the GAMMA platform has enabled the industry's highest capital productivity, while providing the process engineer with the flexibility to include a number of varied applications such as bulk photoresist strip, high dose implant strip, photoresist etchback, and soft silicon etch on the same platform. This article discusses the technical challenges of these processes and describes the product features that enable simple approaches to meeting them without compromising on the system throughput. 

Mark Slezak, JSR Micro, Inc.

ABSTRACT

As critical dimensions continue to shrink, the technical challenges for 193-nm lithography continue to increase. In order for ArF lithography to support the 65-nm node and below, resist suppliers and lithographers will need to identify ways to improve resolution down to half-pitches of 70 nm as well as 70-80 nm isolated trenches and contact hole patterns. Potential line collapse, increased line edge roughness (LER), post-exposure bake (PEB) sensitivity and the need for improved etch resistance are some of the most common issues lithographers face when moving toward the line widths required for the 45-nm node. 

Phillip Walsh, George Li, & A. Forouhi, n&k Technology, Inc.

ABSTRACT

We present a method based on broadband spectrophotometry in conjunction with Forouhi-Bloomer dispersion equations and hybridrigorous coupled wave analysis (RCWA) for monitoring film thickness, film optical properties, trench parameters, and phase shift in phase-shift masks. The method, known as the n&k method, has certain advantages over conventional metrology in terms of throughput and suitability for integration into the mask creation process. At the same time, the n&k method has demonstrated excellent correlation with conventional metrology methods. 

Dr. Peter Kuschnerus, E-Beam Mask Repair Systems, LEO Electron Microscopy Group

ABSTRACT

The quality of photo masks used in chip fabrication is a key factor determining the quality and yield achieved in wafer fabs. In order to achieve reduced feature sizes and to enhance integration depth, shorter wavelengths, i.e. 193nm and 157nm are used. Furthermore, advanced and complex enhancement techniques like optical proximity correction (OPC) features or phase-shift masks (PSM) are necessary. This results in challenging needs for advanced mask repair, in new materials, higher accuracies and precision and higher demands to VUV transmission.  

Mark Osborne, Editor-in-Chief, Semiconductor Fabtech 

ABSTRACT

Lithography technology issues tend to dominate the processing landscape due to their Moore’s Law fulfilment capability. The  Roadmap looked like it was slipping dangerously as 157nm development programs became embroiled in severe technical hurdles, and chip manufacturers were reluctant to commit to multi-million dollar preliminary orders for the next generation of DUV tools. Extending 193nm lithography is rapidly becoming the de facto technology of choice, both for the tool vendor and the chip fabricator. However, a race is on to prove that 193nm Immersion lithography is a viable route that could see 157nm bypassed altogether and allow a straight path
to EUV. At SEMICON West (July 2003), the immersion lithography debate dominated the proceedings with tool vendors jockeying for
position. Here, we review the current state of play, the key challenges and the possible outcome by year-end.

Vivek Bakshi, Jerry Collins, N. V. Edwards, Kevin Kemp, Pat Marmillion, Jan-Peter Urbach, Thomas White & Obert Wood, International SEMATECH

ABSTRACT

The purpose of this article is to provide an update of the current status and most recent advances in each of the specific areas of sources, masks, optics, photoresists and microexposure tool for extreme ultraviolet lithography. The article is therefore organized according to these topics, with a brief discussion of the issues surrounding each, the current development status, and future outlook. A sustained study on the development of industry infrastructure for EUVL is underway at International SEMATECH. Although significant challenges remain, progress is being made on various technical fronts. 

Yuichi Yamada, Canon, Inc. & Toshihiro Oga, Canon U.S.A., Inc.

ABSTRACT

Lithography, the primary enabling technology of the semiconductor industry, is rapidly moving from 130nm to 90nm for volume
production, and 65nm for R&D. Suppliers of lithography systems are being challenged to deliver superior imaging performance at ever-higher productivity at two-year design shrink intervals. To ensure a balance of performance and cost, the manufacturers of leading-edge devices are pursuing a mix-and-match strategy using new very high NA (0.85) 193nm (ArF) scanners for critical layers, 248nm (KrF) for semicritical layers and i-line for non-critical. This paper outlines Canon’s exposure tool strategy for the 90nm to 65nm
era, with emphasis on platform design fundamentals, imaging/machine performance, and cost of ownership.

Ralph R. Dammel, Clariant Corporation, New Jersey, USA

ABSTRACT

The improvements in photoresists required to meet the ITRS roadmap’s goals are discussed for the 100nm node and beyond. The main issues as resist technologies are being introduced at half-wavelength resolution are found to be low DOF, mask error  enhancement factors (MEEF), line edge roughness (LER), line collapse at high aspect ratios, particle and defectivity issues, PEB sensitivity requirements, as well as general polymer physics and chemistry limitations, such as issues related to absorbance and dry etch stability. It is found that while some solutions are on the horizon for the nearer nodes of the roadmap, there are currently no concepts to deal with some of the extremely demanding roadmap goals for the out-years.