V. Vartanian, B-Y Nguyen, A. Thean, D. Zhang, S. Zollner, T. White, M. Sadaka, B. Goolsby, V. Dhandapani, J. Hildreth, L. McCormick, D. Theodore, Q. Xie, X-D Wang, M. Canonico, M. Kottke, Z. Shi, L. Mathew, M. Zavala, C. Parker, H. Collard, L. Prabhu, R. Rai, S. Murphy, P. Montgomery, S. Kalpat, M. Ramon, V. Adams, J. Jiang, J. Chen, V. Kaushik, M. Sadd, A. Barr, A. Vandooren, D. Pham, V. Kolagunta, M. Orlowski, N. Ramani, S. Vanketesan & J. Mogab, Freescale Semiconductor, Inc., Advanced Products Research and Development Laboratory, Austin, Texas, USA

ABSTRACT

The semiconductor industry has traditionally relied on reducing transistor dimensions such as gate length and gate oxide thickness to improve circuit performance. However, as gate lengths are reduced below 30 nm, new materials, processes, and device structures are required to overcome the fundamental physical limitations of conventional transistor materials and designs. 

Amir Al-Bayati, Lori Washington, Li-Qun Xia, Mihaela Balseanu, Zheng Yuan, Mark Kawaguchi,Faran Nouri & Reza Arghavani, Applied Materials, Inc., USA

ABSTRACT

A key method being used to extend Moore's Law to the 45nm node and beyond is to induce local, uniaxial tensile/compressive strain in the channel of a MOSFET to dramatically boost device performance. Three different families of films are the leading approaches for stress induction. Newly developed silicon nitride (SiN) films with stress varying from -3.0GPa to 1.9GPa can induce stress in the channel when used over a gate stack or engineered into STI processing. Tensile and compressive oxides induce further stress when used in STI or post gate stack processing. Finally, the use of selective epitaxial SiGe deposited in recessed/raised source/drain structures is an alternative method of stress induction. 

Kirklen Henson & Malgorzata Jurczak, IMEC, Leuven, Belgium

ABSTRACT

The introduction of metal gates into CMOS technology faces significant challenges. First, appropriate materials and processes must be identified that give the desired symmetry and magnitude of device threshold voltage. Secondly, a cost-effective integration scheme must be developed for manufacturing. Thirdly, the metal-gate solutions should be scalable to future technologies. Achieving symmetric threshold voltages requires multiple work functions: one for the NMOS and one for the PMOS device. 

Professor Peter Ashburn, Director & Technical Advisor, Innos, Southampton, UK Huda El Mubarek, School of Electronics & Computer Science, Southampton University, UK

ABSTRACT

Boron diffuses relatively quickly in silicon at temperatures typically used for anneals in CMOS and bipolar technologies making it hard to precisely control the location of the doping profiles and very difficult to form very shallow boron-doped junctions. This problem is much worse when anneals are carried out after ion implantation because of transient enhanced diffusion, which is caused by damage introduced during ion implantation, and arises because dopants diffuse with the aid of point defects, interstitials in the case of boron. Transient enhanced diffusion can enhance the diffusion coefficient of boron by as much as an order of magnitude during the short anneals typically used in rapid thermal annealing. 

D.E. Joyce & P.A. Ryan, Bede, Durham, UK, & M.Wormington, Bede, Englewood, CO, USA

ABSTRACT

This article describes the use of modern X-ray diffraction equipment in the field of SiGe assessment. Strain, composition and layer thicknesses can all be measured on production wafers, i.e. nondestructively at high spatial resolution and high accuracy. 

C. M. Osburn, A. Kingon, G. Lucovsky, J. P. Maria, V. Misra & G. Parsons,; North Carolina State University & S. A. Campbell, University of Minnesota, E. Eisenbraun, University of Albany, E. Garfunkel & T. Gustafson, Rutgers University, D. L. Kwong & J. Lee, University of Texas at Austin, T. P. Ma, Yale University, D. Schlom, Penn State University, S. Stemmer, UC Santa Barbara

ABSTRACT

Considerable progress has been made in identifying materials and processes for high k gate stacks which meet the ITRS leakage requirements. Nitrided Hafnium silicates have been shown to possess the requisite thermal stability for equivalent oxide thicknesses (EOT) below about 1 nm. Gate electrodes of TaSiN, Ru, or Ru/Ta alloys also appear to meet the stability requirements and possess appropriate work functions. 

Titus Menzies, The Street.com

ABSTRACT

Silicon on insulator (SOI) has been signalled as the solution to deliver higher performing and lower power-consuming semiconductors. Originally geared towards use in military and satellite applications, the industry is looking to use SOI in making mass market DSPs and MPUs, especially in mobile consumer applications. However, key issues cited by 300-mm fab managers are on the pricing and yield rates of 300-mm SOI wafers. This, and the transition to use SOI for mobile applications, has changed the competitive environment. We have analysed IBIS Technology and Soitec, the two leading suppliers of SOI wafers.We have compared the processes of both companies, views from suppliers and customers and possible contracts to be won or lost in the near-term. 

Written by Takako Kimura, Kayo Momoda & Jun Sonobe, Air Liquide Labs., Yoshihiro Ueno, Air Liquide Japan, Jean-Marc Girard, Air Liquide Electronics, Corporate Division

ABSTRACT

This article deals with how to secure a safe and reliable F2 supply at semiconductor manufacturing sites in accordance with the local regulations and the unique circumstances. In order to overcome the drawbacks and concerns of F2 supply, a solution package based on the risk assessment and a material compatibility study is described. As a result a safe, reliable and high-purity F2 supply is available according to the needs of the end user whether by gas cabinet or by on-site generation system, as has been already demonstrated through a continual commercial operation. 

John Baxter, Swagelok Company, Solon, OH, USA 

ABSTRACT 

Perfluoropolyether fluids are being increasingly used as coolants in heat transfer systems for semiconductor applications. However, some users have encountered seal problems with these fluids, resulting in leakage, which is expensive. These problems have been traced to the dynamic O-ring seals in the plug valves commonly used. This article describes a solution to this problem, based on a ball valve with silicone flange seals. 

Wesley E. Sund, Brooks Instrument, Hatfield, PA, USA

ABSTRACT
 
Accurate and reliable liquid flow control is a key success factor in many new semiconductor processes, including chemical-mechanical polishing (CMP). With many flow-sensing technologies being available, selection of the proper technology is dependent on the process requirements. Available flow technologies are reviewed here and capabilities are summarised to assist in the selection process.