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Thin is in: Examining the benefits, challenges of the ultrathin—solar wafer, that is

11 August 2008 | By Tom Cheyney | Chip Shots

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You got your thin wafers, your very thin wafers, and soon your ultrathin wafers. Just how thin is ultrathin? Less than 100 microns, according to Solar Vision Consulting's Andy Skumanich, who discussed the impact of the thinnest silicon slices on the solar manufacturing chain during his recent presentation at Intersolar/Semicon in San Francisco.

Andy is another refugee from the semiconductor world now plying his trade in solar PV. (Shouldn't there be a support group for these ex-chipheads?) I first met him in the late 1990s, during his tenure in what was then Applied Materials' process and diagnostics control group, when he coauthored a technical article for MICRO about chasing down and classifying IC manufacturing defects, on the fly and otherwise, and generally attempting to help chipmakers enhance their yields.

Andy told me his interest in photovoltaics goes back to his grad school days when he wrote his doctoral thesis on defects of another sort--the light-induced ones found in certain amorphous-silicon solar cell/panel technologies. He also worked for silicon-nanoink thin-film PV purveyors Innovalight for awhile after spending two years with Applied's then-nascent solar group and before starting his consultancy.

Thin Wafer

So what's the big deal about thinner and thinner solar wafers? Like so much of PV manufacturing, it's about pushing down those costs per manufactured watt. Once you get below 100 microns, "it's all about saving poly," as in grams per watt of polysilicon, as Andy explained. When the thickness drops from 200 to 100 microns, there's a 30% drop in overall cost. Ultrathins have some other potentially big-time upsides, namely higher conversion efficiencies (at least theoretically) and better flexibility below that 100-micron threshold.

The industry's thinnest wafers are getting to about 180 microns in the best fabs, according to Andy, with companies like SunPower testing around 145-micron thicknesses. On the R&D front, Fraunhofer ISE scientists have successfully fabricated 35-micron-thin wafers with 20% conversion efficiencies. (The accompanying photo came from the ISE site.) Elsewhere, Sanyo has made 70-80-micron-thick research wafers for its HIT cell technology, and IMEC has several wafer-thinning projects under way, including a new method that produces thicknesses in the 30- to 50-micron range on "crystalline silicon foils" that would be adhered to a low-cost carrier substrate.

Can wire-saw technologies take the industry as far as it needs to go? Not likely, thinks Andy, although certain improvements could coax it close to that 100-micron line in the poly sand. The saws generate too much subsurface damage when you get down to that thickness, with 10-20 micron microcracks propagating in the substrate that cancel out the perceived benefits of thinness. There's a significant thickness and throughput tradeoff with the yield hits one would take because of all that not-quite-ultra-thin wafer breakage. Plus there's the continuing problem of what to do with that annoying leftover kerf.

Researchers and developers are hard at work on some alternatives to those diamond-bladed saws, including Fraunhofer and Synova's laser-chemical enhanced cutting approach, plasma cutting at Toyo Advanced Technologies, the silicon-ribbon process used at Evergreen Solar, and the stress-induced liftoff method at IMEC. Andy also showed a couple of slides about the work at a company where he has been spending alot of his consulting time of late: SiGen (Silicon Genesis) and its next-gen wafering "breakthrough," PolyMax.

Although SiGen doesn't want to reveal many details about the process until it officially rolls out its data at the PVSEC event in Valencia, Spain, early next month, Andy did talk a bit about the intriguing kerfless and slurryless technique which uses implantation and cleaving to slice 50-micron and thinner, mechanically robust wafers from monocrystalline silicon boules, with excellent thickness uniformity and lifetime degradation specs.

Like any emerging technology, ultrathin wafers have plenty of issues, especially those of the mechanical kind. Challenges include breakage, saw damage, rampant microcracks, and bowing as well as a drop-off in conversion efficiencies below the century mark, according to Andy, so some new process enhancements are required. On the manufacturing side, the top progress-inhibitors are, first and foremost, wafer handling and manipulation, with texturization and light-trapping a close second.

The handling conundrum is an obvious one, since the automated schlepping of thousands upon thousands of ultrathins with minimal breakage in a solar fab will not be easy. Any failure to keep the wince-inducing sounds of cracking/breaking wafers to BAM (bare-ass minimum) levels has yield, reliability, and system optimization consequences.

The texturization/light-trapping issue revolves around preventing a fall-off in efficiencies, with a method needed for reducing the etched-off amount of silicon on each side, which is often in the 20-micron range. In the plus column, he cited BP Solar's use of isochemical etch, or ICE, which removes less material and offers improved optical absorption performance.

In terms of how the grid and back-contact layers and films are applied, Andy noted a need for finer and/or noncontact structures in light of the less-than-ideal conductive contact results from ink-jet printing techniques. Fraunhofer and Xerox PARC are researching two-layer and printed metallization, respectively, and Komax Systems has studied wafer breakage extensively, especially in the screen printing, tabbing, and stringing realms.

Controlling the wafer-thinning process faces obstacles like keeping the actual thickness consistent, since variable wafer widths lead to degraded contact quality. Even if flexibility has its advantages, bowing can be a problem, but process changes and new pastes can help reduce the lack of uniform flatness.

One area that will continue to plague the ultrathins will be those pesky hidden/undetected microcracks, generated during wire sawing or laser cutting and spreading during several subsequent processing steps (diffusion, screen printing, back-contact firing, soldering, lamination, etc.). The potential multimillion-dollar hit to the industry if compromised ultrathin wafers start ending up in finished modules in any numbers, with that percentage likely to rise as the substrates get even thinner, caused Andy to stress the necessity of coming up with new, in-line ways to prevent or detect microcracks before they wreak havoc.

(Hello, semiconductor defect inspection/review and metrology tool companies, do you read me, over? We have a potential market opportunity here!)

As wafer thicknesses continue to shrink, there are implications all along the solar manufacturing chain--from how the wafers are cut, to how they are handled and processed during the cell-making steps, to those cells' integration and encapsulation into modules and eventual installation in all flavors of system arrays. The advent of the ultrathin wafer will be one of the defining challenges for the equipment/materials supply chain and the cell and module manufacturers as the photovoltaics industry transitions to the next tier of advanced technologies and reduced cost structures.

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